參數(shù)資料
型號(hào): XQ2V6000-4BG728N
廠商: Xilinx, Inc.
英文描述: QPro Virtex-II 1.5V Military QML Platform FPGAs
中文描述: QPro的Virtex - II 1.5V的軍事QML第平臺(tái)FPGA
文件頁(yè)數(shù): 27/128頁(yè)
文件大小: 2738K
代理商: XQ2V6000-4BG728N
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QPro Virtex-II 1.5V Military QML Platform FPGAs
DS122 (v1.1) January 7, 2004
Product Specification
www.xilinx.com
1-800-255-7778
27
R
18 Kbit Block SelectRAM
Resources
Introduction
Virtex-II devices incorporate large amounts of 18 Kbit block
SelectRAM. These complement the distributed SelectRAM
resources that provide shallow RAM structures imple-
mented in CLBs. Each Virtex-II block SelectRAM is an 18
Kbit true dual-port RAM with two independently clocked and
independently controlled synchronous ports that access a
common storage area. Both ports are functionally identical.
CLK, EN, WE, and SSR polarities are defined through con-
figuration.
Each port has the following types of inputs: Clock and Clock
Enable, Write Enable, Set/Reset, and Address, as well as
separate Data/parity data inputs (for writes) and Data/parity
data outputs (for reads).
Operation is synchronous. The block SelectRAM behaves
like a register. Control, address, and data inputs must (and
need only) be valid during the set-up time window prior to a
rising (or falling, a configuration option) clock edge. Data
outputs change as a result of the same clock edge.
Configuration
The Virtex-II block SelectRAM supports various configura-
tions, including single- and dual-port RAM and various
data/address aspect ratios. Supported memory configura-
tions for single- and dual-port modes are shown in
Table 18
.
Single-Port Configuration
As a single-port RAM, the block SelectRAM has access to
the 18 Kbit memory locations in any of the 2K x 9-bit,
1K x 18-bit, or 512 x 36-bit configurations and to 16 Kbit
memory locations in any of the 16K x 1-bit, 8K x 2-bit, or
4K x 4-bit configurations. The advantage of 9-bit, 18-bit,
and 36-bit widths is the ability to store a parity bit for every
eight bits. Parity bits must be generated or checked exter-
nally in user logic. In such cases, the width is viewed as 8 +
1, 16 + 2, or 32 + 4. These extra parity bits are stored and
behave exactly as the other bits, including the timing param-
eters. Video applications can use the 9-bit ratio of Virtex-II
block SelectRAM memory to advantage.
Each block SelectRAM cell is a fully synchronous memory,
as illustrated in
Figure 30
. Input data bus and output data
bus widths are identical.
Dual-Port Configuration
As a dual-port RAM, each port of block SelectRAM has
access to a common 18 Kbit memory resource. These are
fully synchronous ports with independent control signals for
each port. The data widths of the two ports can be config-
ured independently, providing built-in bus-width conversion.
Table 17:
Virtex-II Logic Resources Available in All CLBs
Device
CLB Array:
Row x
Column
Number
of
Slices
Number
of
LUTs
Max Distributed
SelectRAM or Shift
Register (bits)
Number
of
Flip-Flops
Number
of
Carry Chains
(1)
Number
of SOP
Chains
(1)
XQ2V1000
40 x 32
5,120
10,240
163,840
10,240
64
80
XQ2V3000
64 x 56
14,336
28,672
458,752
28,672
112
128
XQ2V6000
96 x 88
33,792
67,584
1,081,344
67,584
176
192
Notes:
1.
The carry chains and SOP chains can be split or cascaded.
Table 18:
Dual- and Single-Port Configurations
16K x 1 bit
2K x 9 bits
8K x 2 bits
1K x 18 bits
4K x 4 bits
512 x 36 bits
Figure 30:
18 Kbit Block SelectRAM Memory in
Single-Port Mode
DOP
DIP
ADDR
WE
EN
SSR
CLK
18 Kbit Block SelectRAM
DS031_10_071602
DI
DO
ds122_1_1.fm Page 27 Wednesday, January 7, 2004 9:15 PM
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