- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375045 > XQ2V3000-4CG717M (XILINX INC) QPro Virtex-II 1.5V Military QML Platform FPGAs PDF資料下載
參數(shù)資料
| 型號(hào)： | XQ2V3000-4CG717M |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| 中文描述： | FPGA, 3584 CLBS, 3000000 GATES, 650 MHz, CBGA717 |
| 封裝： | CERAMIC, CGA-717 |
| 文件頁(yè)數(shù)： | 43/128頁(yè) |
| 文件大小： | 2738K |
| 代理商： | XQ2V3000-4CG717M |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)當(dāng)前第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)
QPro Virtex-II 1.5V Military QML Platform FPGAs
DS122 (v1.1) January 7, 2004
Product Specification
www.xilinx.com
1-800-255-7778
43
R
tion. By default, HSWAP_EN is tied High (internal pull-up),
which shuts off the pull-ups on the user I/O pins during con-
figuration. When HSWAP_EN is tied Low, user I/Os have
pull-ups during configuration. Other dedicated pins are
CCLK (the configuration clock pin), DONE, PROG_B, and
the boundary-scan pins: TDI, TDO, TMS, and TCK.
Depending on the configuration mode chosen, CCLK can
be an output generated by the FPGA, or an input accepting
an externally generated clock. The configuration pins and
boundary-scan pins are independent of the V
CCO
. The aux-
iliary power supply (V
CCAUX
) of 3.3V is used for these pins.
All configuration pins are LVTTL 12 mA. (See
QPro Virtex-II
DC Characteristics
.)
A persist option is available which can be used to force the
configuration pins to retain their configuration function even
after device configuration is complete. If the persist option is
not selected, then the configuration pins with the exception
of CCLK, PROG_B, and DONE can be used as user I/O in
normal operation. The persist option does not apply to the
boundary-scan related pins. The persist feature is valuable
in applications which employ partial reconfiguration or
reconfiguration on the fly.
Configuration Modes
Virtex-II supports the following five configuration modes:
Slave-serial mode
Master-serial mode
Slave SelectMAP mode
Master SelectMAP mode
Boundary-Scan mode (IEEE 1532/IEEE 1149)
A detailed description of configuration modes is provided in
the
Virtex-II User Guide
(
UG002
).
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other serial source
of configuration data. The CCLK pin on the FPGA is an
input in this mode. The serial bitstream must be setup at the
DIN input pin a short time before each rising edge of the
externally generated CCLK.
Multiple FPGAs can be daisy chained for configuration from
a single source. After a particular FPGA has been config-
ured, the data for the next device is routed internally to the
DOUT pin. The data on the DOUT pin changes on the rising
edge of CCLK.
Slave-serial mode is selected by applying <111> to the
mode pins (M2, M1, M0). A weak pull-up on the mode pins
makes slave serial the default mode if the pins are left
unconnected.
Master-Serial Mode
In master-serial mode, the CCLK pin is an output pin. It is
the Virtex-II FPGA device that drives the configuration clock
on the CCLK pin to a Xilinx Serial PROM, which in turn
feeds bit-serial data to the DIN input. The FPGA accepts
this data on each rising CCLK edge. After the FPGA has
been loaded, the data for the next device in a daisy chain is
presented on the DOUT pin after the rising CCLK edge.
The interface is identical to slave serial except that an inter-
nal oscillator is used to generate the configuration clock
(CCLK). A wide range of frequencies can be selected for
CCLK, which always starts at a slow default frequency. Con-
figuration bits then switch CCLK to a higher frequency for
the remainder of the configuration.
Slave SelectMAP Mode
The SelectMAP mode is the fastest configuration option.
Byte-wide data is written into the Virtex-II FPGA device with
a BUSY flag controlling the flow of data. An external data
source provides a byte stream, CCLK, an active-Low Chip
Select (CS_B) signal, and a Write signal (RDWR_B). If
BUSY is asserted (High) by the FPGA, the data must be
held until BUSY goes Low. Data can also be read using the
SelectMAP mode. If RDWR_B is asserted, configuration
data is read out of the FPGA as part of a readback opera-
tion.
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained to permit high-speed 8-bit readback using the per-
sist option.
Multiple Virtex-II FPGAs can be configured using the
SelectMAP mode, and can be made to start-up simulta-
neously. To configure multiple devices in this way, wire the
individual CCLK, Data, RDWR_B, and BUSY pins of all the
devices in parallel. The individual devices are loaded sepa-
rately by deasserting the CS_B pin of each device in turn
and writing the appropriate data.
Master SelectMAP Mode
This mode is a master version of the SelectMAP mode. The
device is configured byte-wide on a CCLK supplied by the
Virtex-II FPGA. Timing is similar to the Slave SerialMAP
mode except that CCLK is supplied by the Virtex-II FPGA.
Boundary-Scan (JTAG, IEEE 1532) Mode
In boundary-scan mode, dedicated pins are used for config-
uring the Virtex-II device. The configuration is done entirely
through the IEEE 1149.1 Test Access Port (TAP). Virtex-II
device configuration using boundary scan is compliant with
IEEE 1149.1-1993 standard and the new IEEE 1532 stan-
dard for In-System Configurable (ISC) devices. The IEEE
1532 standard is backward compliant with the IEEE
1149.1-1993 TAP and state machine. The IEEE Standard
1532 for In-System Configurable (ISC) devices is intended
to be programmed, reprogrammed, or tested on the board
via a physical and logical protocol.
Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes.
ds122_1_1.fm Page 43 Wednesday, January 7, 2004 9:15 PM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XQ2V3000-4CG717N | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V3000-4FG456M | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V3000-4FG456N | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V6000 | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V6000-4BG575M | QPro Virtex-II 1.5V Military QML Platform FPGAs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XQ2V3000-4CG717N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V3000-4FG456M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V3000-4FG456N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V3000-BG575I | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Platform FPGAs |
| XQ2V3000-BG575M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Platform FPGAs |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。