參數(shù)資料
型號(hào): XQ2V3000-4CG717M
廠商: XILINX INC
元件分類: FPGA
英文描述: QPro Virtex-II 1.5V Military QML Platform FPGAs
中文描述: FPGA, 3584 CLBS, 3000000 GATES, 650 MHz, CBGA717
封裝: CERAMIC, CGA-717
文件頁數(shù): 30/128頁
文件大小: 2738K
代理商: XQ2V3000-4CG717M
QPro Virtex-II 1.5V Military QML Platform FPGAs
30
www.xilinx.com
1-800-255-7778
DS122 (v1.1) January 7, 2004
Product Specification
R
Control Pins and Attributes
Virtex-II SelectRAM memory has two independent ports
with the control signals described in
Table 21
. All control
inputs including the clock have an optional inversion.
Initial memory content is determined by the INIT_xx
attributes. Separate attributes determine the output register
value after device configuration (INIT) and SSR is asserted
(SRVAL). Both attributes (INIT_B and SRVAL) are available
for each port when a block SelectRAM resource is config-
ured as dual-port RAM.
Locations
Virtex-II SelectRAM memory blocks are located in either
four or six columns. The number of blocks per column
depends of the device array size and is equivalent to the
number of CLBs in a column divided by four. Column loca-
tions are shown in
Table 22
.
Figure 34:
NO_CHANGE Mode
CLK
WE
Data_in
Data_in
New
aa
Last Read Cycle Content (no change)
Address
Internal
Memory
DO
No change during write
Data_out
DI
DS031_12_102000
RAM Contents
New
Old
Table 21:
Control Functions
Control Signal
Function
CLK
Read and Write Clock
EN
Enable affects Read, Write, Set, Reset
WE
Write Enable
SSR
Set DO register to SRVAL (attribute)
Table 22:
SelectRAM Memory Floor Plan
Device
Columns
SelectRAM Blocks
Per Column
Total
XQ2V1000
4
10
40
XQ2V3000
6
16
96
XQ2V6000
6
24
144
ds122_1_1.fm Page 30 Wednesday, January 7, 2004 9:15 PM
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