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| 型號： | XQ2V3000-4CF1144N |
| 廠商： | Xilinx, Inc. |
| 英文描述： | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| 中文描述： | QPro的Virtex - II 1.5V的軍事QML第平臺FPGA |
| 文件頁數(shù)： | 26/128頁 |
| 文件大?。?/td> | 2738K |
| 代理商： | XQ2V3000-4CF1144N |
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QPro Virtex-II 1.5V Military QML Platform FPGAs
26
www.xilinx.com
1-800-255-7778
DS122 (v1.1) January 7, 2004
Product Specification
R
3-State Buffers
Introduction
Each Virtex-II CLB contains two 3-state drivers (TBUFs)
that can drive on-chip buses. Each 3-state buffer has its
own 3-state control pin and its own input pin.
Each of the four slices have access to the two 3-state buff-
ers through the switch matrix, as shown in
Figure 28
.
TBUFs in neighboring CLBs can access slice outputs by
direct connects. The outputs of the 3-state buffers drive hor-
izontal routing resources used to implement 3-state buses.
The 3-state buffer logic is implemented using AND-OR logic
rather than 3-state drivers, so that timing is more predict-
able and less load dependent especially with larger devices.
Locations/Organization
Four horizontal routing resources per CLB are provided for
on-chip 3-state buses. Each 3-state buffer has access alter-
nately to two horizontal lines, which can be partitioned as
shown in
Figure 29
. The switch matrices corresponding to
SelectRAM memory and multiplier or I/O blocks are
skipped.
Number of 3-State Buffers
Table 15
shows the number of 3-state buffers available in
each Virtex-II device. The number of 3-state buffers is twice
the number of CLB elements.
CLB/Slice Configurations
Table 16
summarizes the logic resources in one CLB. All of
the CLBs are identical and each CLB or slice can be imple-
mented in one of the configurations listed.
Table 17
shows
the available resources in all CLBs.
Figure 28:
Virtex-II 3-State Buffers
Slice
S3
Slice
S2
Slice
S1
Slice
S0
Switch
Matrix
DS031_37_060700
TBUF
TBUF
Table 15:
Virtex-II 3-State Buffers
Device
3-State Buffers
per Row
Total Number
of 3-State Buffers
XQ2V1000
64
2,560
XQ2V3000
112
7,168
XQ2V6000
176
16,896
Figure 29:
3-State Buffer Connection to Horizontal Lines
Switch
matrix
CLB-II
Switch
matrix
CLB-II
DS031_09_032700
Programmable
connection
3 - state lines
Table 16:
Logic Resources in One CLB
Slices
LUTs
Flip-Flops
MULT_ANDs
Arithmetic &
Carry Chains
SOP
Chains
Distributed
SelectRAM
Shift
Registers
TBUF
4
8
8
8
2
2
128 bits
128 bits
2
ds122_1_1.fm Page 26 Wednesday, January 7, 2004 9:15 PM
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XQ2V3000-4CG717M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Platform FPGAs |
| XQ2V3000-4CG717N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V3000-4FG456M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V3000-4FG456N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V3000-BG575I | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Platform FPGAs |
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