參數(shù)資料
型號： XQ2V3000-4BG728N
廠商： XILINX INC
元件分類： FPGA
英文描述： QPro Virtex-II 1.5V Military QML Platform FPGAs
中文描述： FPGA, 3584 CLBS, 3000000 GATES, 650 MHz, PBGA728
封裝： 1.27 MM PITCH, MS-034BAR-1, BGA-728
文件頁數(shù)： 69/128頁
文件大?。?/td> 2738K
代理商： XQ2V3000-4BG728N
QPro Virtex-II 1.5V Military QML Platform FPGAs
DS122 (v1.1) January 7, 2004
Product Specification
www.xilinx.com
1-800-255-7778
69
R
DCM Timing Parameters
All devices are 100% functionally tested. Because of the dif-
ficulty in directly measuring many internal timing parame-
ters, those parameters are derived from benchmark timing
patterns. The following guidelines reflect worst-case values
across the recommended operating conditions. All output
jitter and phase specifications are determined through sta-
tistical measurement at the package pins.
Operating Frequency Ranges
Table 61:
Operating Frequency Ranges
Description
Symbol
Constraints
Value
Units
Output Clocks (Low Frequency Mode)
CLK0, CLK90, CLK180, CLK270
CLKOUT_FREQ_1X_LF_Min
24.00
MHz
CLKOUT_FREQ_1X_LF_Max
180.00
MHz
CLK2X, CLK2X180
CLKOUT_FREQ_2X_LF_Min
48.00
MHz
CLKOUT_FREQ_2X_LF_Max
360.00
MHz
CLKDV
CLKOUT_FREQ_DV_LF_Min
1.50
MHz
CLKOUT_FREQ_DV_LF_Max
120.00
MHz
CLKFX, CLKFX180
CLKOUT_FREQ_FX_LF_Min
24.00
MHz
CLKOUT_FREQ_FX_LF_Max
210.00
MHz
Input Clocks (Low Frequency Mode)
CLKIN (using DLL outputs)
(1), (3)
CLKIN_FREQ_DLL_LF_Min
24.00
MHz
CLKIN_FREQ_DLL_LF_Max
180.00
MHz
CLKIN (using CLKFX outputs)
(2), (3)
CLKIN_FREQ_FX_LF_Min
1.00
MHz
CLKIN_FREQ_FX_LF_Max
210.00
MHz
PSCLK
PSCLK_FREQ_LF_Min
0.01
MHz
PSCLK_FREQ_LF_Max
360.00
MHz
Output Clocks (High Frequency Mode)
CLK0, CLK180
CLKOUT_FREQ_1X_HF_Min
48.00
MHz
CLKOUT_FREQ_1X_HF_Max
360.00
MHz
CLKDV
CLKOUT_FREQ_DV_HF_Min
3.00
MHz
CLKOUT_FREQ_DV_HF_Max
240.00
MHz
CLKFX, CLKFX180
CLKOUT_FREQ_FX_HF_Min
210.00
MHz
CLKOUT_FREQ_FX_HF_Max
270.00
MHz
Input Clocks (High Frequency Mode)
CLKIN (using DLL outputs)
(1), (3)
CLKIN_FREQ_DLL_HF_Min
48.00
MHz
CLKIN_FREQ_DLL_HF_Max
360.00
MHz
CLKIN (using CLKFX outputs)
(2), (3)
CLKIN_FRQ_FX_HF_Min
50.00
MHz
CLKIN_FRQ_FX_HF_Max
270.00
MHz
PSCLK
PSCLK_FREQ_HF_Min
0.01
MHz
PSCLK_FREQ_HF_Max
360.00
MHz
Notes:
1.
2.
3.
“DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
If both DLL and CLKFX outputs are used, follow the more restrictive specification.
If the CLKIN_DIVIDE_BY_2 attribute of the DCM is used, then double these values.
ds122_1_1.fm Page 69 Wednesday, January 7, 2004 9:15 PM
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