參數(shù)資料
型號(hào)： XQ2V3000-4BG575N
廠商： Xilinx, Inc.
英文描述： QPro Virtex-II 1.5V Military QML Platform FPGAs
中文描述： QPro的Virtex - II 1.5V的軍事QML第平臺(tái)FPGA
文件頁數(shù)： 67/128頁
文件大?。?/td> 2738K
代理商： XQ2V3000-4BG575N
QPro Virtex-II 1.5V Military QML Platform FPGAs
DS122 (v1.1) January 7, 2004
Product Specification
www.xilinx.com
1-800-255-7778
67
R
QPro Virtex-II Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate,
with
DCM
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate,
without
DCM
Table 57:
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate,
with
DCM
Description
Symbol
Device
Value
Units
LVTTL Global Clock Input to Output delay using Output flip-flop,
12 mA, Fast Slew Rate,
with
DCM.
For data
output
with different standards, adjust the delays with the
values shown in
IOB Output Switching Characteristics Standard
Adjustments
, page 56
.
Global Clock and OFF with DCM
T
ICKOFDCM
XQ2V1000
2.76
ns
XQ2V3000
2.88
ns
XQ2V6000
3.45
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured with a 35 pF external capacitive load. The only time it is not 50% of V
CC
threshold is with LVCMOS. For
other I/O standards and different loads, see
Table 47
.
DCM output jitter is included in the measurement.
2.
3.
Table 58:
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate,
without
DCM
Description
Symbol
Device
Value
Units
LVTTL Global Clock Input to Output Delay using Output flip-flop,
12 mA, Fast Slew Rate,
without
DCM.
For data
output
with different standards, adjust the delays with the
values shown in
IOB Output Switching Characteristics Standard
Adjustments
, page 56
.
Global Clock and OFF without DCM
T
ICKOF
XQ2V1000
5.90
ns
XQ2V3000
6.62
ns
XQ2V6000
7.22
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at 50% V
CC
threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
Table 47
.
2.
ds122_1_1.fm Page 67 Wednesday, January 7, 2004 9:15 PM
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