參數(shù)資料
型號(hào): XQ2V3000-4BG575N
廠商: Xilinx, Inc.
英文描述: QPro Virtex-II 1.5V Military QML Platform FPGAs
中文描述: QPro的Virtex - II 1.5V的軍事QML第平臺(tái)FPGA
文件頁(yè)數(shù): 14/128頁(yè)
文件大小: 2738K
代理商: XQ2V3000-4BG575N
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QPro Virtex-II 1.5V Military QML Platform FPGAs
14
www.xilinx.com
1-800-255-7778
DS122 (v1.1) January 7, 2004
Product Specification
R
High pin count packages (especially ball grid arrays) can
not accommodate external termination resistors.
Virtex-II XCITE DCI provides controlled impedance drivers
and on-chip termination for single-ended and differential
I/Os. This eliminates the need for external resistors, and
improves signal integrity. The DCI feature can be used on
any IOB by selecting one of the DCI I/O standards.
When applied to inputs, DCI provides input parallel termina-
tion. When applied to outputs, DCI provides controlled
impedance drivers (series termination) or output parallel
termination.
DCI operates independently on each I/O bank. When a DCI
I/O standard is used in a particular I/O bank, external refer-
ence resistors must be connected to two dual-function pins
on the bank. These resistors, the voltage reference of the N
transistor (VRN), and the voltage reference of the P transis-
tor (VRP) are shown in
Figure 10
.
When used with a terminated I/O standard, the value of
resistors are specified by the standard (typically 50
).
When used with a controlled impedance driver, the resistors
set the output impedance of the driver within the specified
range (25
to 100
)
. For all series and parallel termina-
tions listed in
Table 11
and
Table 12
, the reference resistors
must have the same value for any given bank. One percent
resistors are recommended.
The DCI system adjusts the I/O impedance to match the two
external reference resistors or half of the reference resis-
tors, and compensates for impedance changes due to volt-
age and/or temperature fluctuations. The adjustment is
done by turning parallel transistors in the IOB on or off.
Controlled Impedance Drivers (Series
Termination)
DCI can be used to provide a buffer with a controlled output
impedance. It is desirable for this output impedance to
match the transmission line impedance (Z). Virtex-II input
buffers also support LVDCI and LVDCI_DV2 I/O standards.
Controlled Impedance Drivers (Parallel
Termination)
DCI also provides on-chip termination for SSTL3, SSTL2,
HSTL (Class I, II, III, or IV), and GTL/GTLP receivers or
transmitters on bidirectional lines.
Table 12
lists the on-chip parallel terminations available in
Virtex-II devices. V
CCO
must be set according to
Table 8
.
Note that there is a V
CCO
requirement for GTL_DCI and
GTLP_DCI, due to the on-chip termination resistor.
Figure 10:
DCI in a Virtex-II
Bank
DS031_50_101200
VCCO
GND
DCI
DCI
DCI
DCI
VRN
VRP
1 Bank
R
REF
(1%)
R
REF
(1%)
Figure 11:
Internal Series Termination
Table 11:
SelectI/O-Ultra Controlled Impedance Buffers
V
CCO
3.3 V
DCI
DCI Half Impedance
LVDCI_33
LVDCI_DV2_33
2.5 V
LVDCI_25
LVDCI_DV2_25
1.8 V
LVDCI_18
LVDCI_DV2_18
1.5 V
LVDCI_15
LVDCI_DV2_15
Table 12:
SelectI/O-Ultra Buffers with On-Chip Parallel
Termination
I/O Standard
External
Termination
On-Chip
Termination
SSTL3 Class I
SSTL3_I
SSTL3_I_DCI
(1)
SSTL3 Class II
SSTL3_II
SSTL3_II_DCI
(1)
SSTL2 Class I
SSTL2_I
SSTL2_I_DCI
(1)
SSTL2 Class II
SSTL2_II
SSTL2_II_DCI
(1)
HSTL Class I
HSTL_I
HSTL_I_DCI
HSTL Class II
HSTL_II
HSTL_II_DCI
HSTL Class III
HSTL_III
HSTL_III_DCI
HSTL Class IV
HSTL_IV
HSTL_IV_DCI
Z
IOB
Z
Virtex-II DCI
DS031_51_110600
V
CCO
= 3.3 V, 2.5 V, 1.8 V or 1.5 V
ds122_1_1.fm Page 14 Wednesday, January 7, 2004 9:15 PM
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