參數(shù)資料
型號： XQ2V1000-4CF1144N
廠商： Xilinx, Inc.
英文描述： QPro Virtex-II 1.5V Military QML Platform FPGAs
中文描述： QPro的Virtex - II 1.5V的軍事QML第平臺FPGA
文件頁數(shù)： 34/128頁
文件大?。?/td> 2738K
代理商： XQ2V1000-4CF1144N
QPro Virtex-II 1.5V Military QML Platform FPGAs
34
www.xilinx.com
1-800-255-7778
DS122 (v1.1) January 7, 2004
Product Specification
R
Each global clock buffer can be driven by either the clock
pad to distribute a clock directly to the device, or the Digital
Clock Manager (DCM), discussed in
Digital Clock Man-
ager (DCM)
, page 36
. Each global clock buffer can also be
driven by local interconnects. The DCM has clock output(s)
that can be connected to global clock buffer inputs, as
shown in
Figure 40
.
Global clock buffers are used to distribute the clock to some
or all synchronous logic elements (such as registers in
CLBs and IOBs, and SelectRAM blocks).
Eight global clocks can be used in each quadrant of the
Virtex-II device. Designers should consider the clock distri-
bution detail of the device prior to pin-locking and floorplan-
ning (see the
Virtex-II User Guide,
UG002
).
Figure 42
shows clock distribution in Virtex-II devices.
In each quadrant, up to eight clocks are organized in clock
rows. A clock row supports up to 16 CLB rows (eight up and
eight down). For the largest devices a new clock row is
added, as necessary.
To reduce power consumption, any unused clock branches
remain static.
Global clocks are driven by dedicated clock buffers (BUFG),
which can also be used to gate the clock (BUFGCE) or to
multiplex between two independent clock inputs (BUFG-
MUX).
The most common configuration option of this element is as
a buffer. A BUFG function in this (global buffer) mode, is
shown in
Figure 41
.
The Virtex-II global clock buffer BUFG can also be config-
ured as a clock enable/disable circuit (
Figure 43
), as well as
a two-input clock multiplexer (
Figure 44
). A functional
description of these two options is provided below. Each of
them can be used in either of two modes, selected by con-
figuration: rising clock edge or falling clock edge.
Figure 40:
Virtex-II Clock Distribution Configurations
Clock
Pad
Clock
Buffer
I
0
Clock Distribution
Clock
Pad
Clock
Buffer
I
0
Clock Distribution
CLKIN
CLKOUT
DCM
DS031_43_101000
Figure 41:
Virtex-II BUFG Function
O
I
BUFG
DS031_61_101200
Figure 42:
Virtex-II Clock Distribution
8
8
8
8
NW
NW
NE
SW
SE
NE
SW
SE
DS031_45_120200
8 BUFGMUX
8 BUFGMUX
8 max
8 BUFGMUX
8 BUFGMUX
16 Clocks
16 Clocks
ds122_1_1.fm Page 34 Wednesday, January 7, 2004 9:15 PM
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