參數(shù)資料
型號: XPC860TZP66D4
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 240 x 64 pixel format, CFL, LED, or EL Backlight available
中文描述: 32-BIT, 66 MHz, RISC PROCESSOR, PBGA357
封裝: PLASTIC, BGA-357
文件頁數(shù): 58/76頁
文件大?。?/td> 857K
代理商: XPC860TZP66D4
58
MPC860 Family Hardware Specifications
MOTOROLA
Ethernet Electrical Specifications
Figure 11-57. Ethernet Collision Timing Diagram
Figure 11-58. Ethernet Receive Timing Diagram
134
TENA inactive delay (from TCLK1 rising edge)
10
50
ns
135
RSTRT active delay (from TCLK1 falling edge)
10
50
ns
136
RSTRT inactive delay (from TCLK1 falling edge)
10
50
ns
137
REJECT width low
1
CLK
138
CLKO1 low to SDACK asserted
2
20
ns
139
CLKO1 low to SDACK negated
2
20
ns
1
The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater or equal to 2/1.
2
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
Table 11-20. Ethernet Timing (continued)
Num
Characteristic
All Frequencies
Unit
Min
Max
CLSN(CTS1)
120
(Input)
RCLK1
121
RxD1
(Input)
121
RENA(CD1)
(Input)
125
124
123
127
126
Last Bit
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