參數(shù)資料
型號(hào): XPC860SRZP80D4
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: Family Hardware Specifications
中文描述: 32-BIT, 80 MHz, RISC PROCESSOR, PBGA357
封裝: PLASTIC, BGA-357
文件頁數(shù): 59/76頁
文件大小: 857K
代理商: XPC860SRZP80D4
MOTOROLA
MPC860 Family Hardware Specifications
59
Ethernet Electrical Specifications
Figure 11-59. Ethernet Transmit Timing Diagram
Figure 11-60. CAM Interface Receive Start Timing Diagram
Figure 11-61. CAM Interface REJECT Timing Diagram
TCLK1
128
TxD1
(Output)
128
TENA(RTS1)
(Input)
NOTES:
1.
2.
Transmit clock invert (TCI) bit in GSMR is set.
If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
RENA(CD1)
(Input)
(NOTE 2)
133
134
132
131
121
129
RCLK1
RxD1
(Input)
RSTRT
(Output)
0
136
125
1
1
BIT1
BIT2
Start Frame
REJECT
137
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