參數(shù)資料
型號: XPC860PZP50D4
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: Circular Connector; No. of Contacts:5; Series:; Body Material:Aluminum; Connecting Termination:Solder; Connector Shell Size:18; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:18-5
中文描述: 32-BIT, 50 MHz, RISC PROCESSOR, PBGA357
封裝: PLASTIC, BGA-357
文件頁數(shù): 64/76頁
文件大?。?/td> 857K
代理商: XPC860PZP50D4
64
MPC860 Family Hardware Specifications
MOTOROLA
I2C AC Electrical Specifications
11.11I
2
C AC Electrical Specifications
Table 11-24 provides the I
2
C (SCL < 100 kHz) timings.
Table 11-24. I
2
C Timing (SCL < 100 kH
Z
)
Table 11-25 provides the I
2
C (SCL > 100 kHz) timings.
Table 11-25. . I
2
C Timing (SCL > 100 kH
Z
)
Num
Characteristic
All Frequencies
Unit
Min
Max
200
SCL clock frequency (slave)
0
100
kHz
200
SCL clock frequency (master)
1
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3
×
pre_scaler
×
2).
The ratio SYNCCLK/(BRGCLK / pre_scaler) must be greater or equal to 4/1.
1.5
100
kHz
202
Bus free time between transmissions
4.7
μ
s
203
Low period of SCL
4.7
μ
s
204
High period of SCL
4.0
μ
s
205
Start condition setup time
4.7
μ
s
206
Start condition hold time
4.0
μ
s
207
Data hold time
0
μ
s
208
Data setup time
250
ns
209
SDL/SCL rise time
1
μ
s
210
SDL/SCL fall time
300
ns
211
Stop condition setup time
4.7
μ
s
Num
Characteristic
Expression
All Frequencies
Unit
Min
Max
200
SCL clock frequency (slave)
fSCL
0
BRGCLK/48
Hz
200
SCL clock frequency (master)
1
fSCL
BRGCLK/16512
BRGCLK/48
Hz
202
Bus free time between transmissions
1/(2.2 * fSCL)
s
203
Low period of SCL
1/(2.2 * fSCL)
s
204
High period of SCL
1/(2.2 * fSCL)
s
205
Start condition setup time
1/(2.2 * fSCL)
s
206
Start condition hold time
1/(2.2 * fSCL)
s
207
Data hold time
0
s
208
Data setup time
1/(40 * fSCL)
s
209
SDL/SCL rise time
1/(10 * fSCL)
s
210
SDL/SCL fall time
1/(33 * fSCL)
s
211
Stop condition setup time
1/2(2.2 * fSCL)
s
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