參數(shù)資料
型號(hào): XPC860DPCZP50D4
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: Family Hardware Specifications
中文描述: 32-BIT, 50 MHz, RISC PROCESSOR, PBGA357
封裝: PLASTIC, BGA-357
文件頁數(shù): 65/76頁
文件大?。?/td> 857K
代理商: XPC860DPCZP50D4
MOTOROLA
MPC860 Family Hardware Specifications
65
UTOPIA AC Electrical Specifications
Figure 11-67 shows the I
2
C bus timing.
Figure 11-67. I
2
C Bus Timing Diagram
Part XII UTOPIA AC Electrical Specifications
Table 12-26 shows the AC electrical specifications for the UTOPIA interface.
Figure 12-68 shows signal timings during UTOPIA receive operations.
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3)
×
pre_scaler
×
2).
The ratio SYNCCLK/(BRGCLK / pre_scaler) must be greater or equal to 4/1.
Table 12-26. UTOPIA AC Electrical Specifications
Num
Signal Characteristic
Direction
Min
Max
Unit
U1
UtpClk rise/fall time (Internal clock option)
Output
3.5
ns
Duty cycle
50
50
%
Frequency
50
MHz
U1a
UtpClk rise/fall time (external clock option)
Input
3.5
ns
Duty cycle
40
60
%
Frequency
50
MHz
U2
RxEnb and TxEnb active delay
Output
2
16
ns
U3
UTPB, SOC, Rxclav and Txclav setup time
Input
8
ns
U4
UTPB, SOC, Rxclav and Txclav hold time
Input
1
ns
U5
UTPB, SOC active delay (and PHREQ and PHSEL active delay
in MPHY mode)
Output
2
16
ns
SCL
202
205
203
207
204
208
206
209
211
210
SDA
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