參數(shù)資料
型號(hào)： XPC750EC
英文描述： XPC750P/D XPC750P RISC Microprocessor Hardware Specifications
中文描述： XPC750P /數(shù)XPC750P RISC微處理器硬件規(guī)格
文件頁(yè)數(shù)： 18/52頁(yè)
文件大小： 1274K
代理商： XPC750EC
18
MPC755 RISC Microprocessor Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Figure 8 shows the L2 bus input timing diagrams for the MPC755.
Figure 8. L2 Bus Input Timing Diagrams
Figure 9 shows the L2 bus output timing diagrams for the MPC755.
Figure 9. L2 Bus Output Timing Diagrams
L2SYNC_IN to high impedance:
All outputs when L2CR[14–15] = 00
All outputs when L2CR[14–15] = 01
All outputs when L2CR[14–15] = 10
All outputs when L2CR[14–15] = 11
t
L2CHOZ
—
—
—
—
2.4
2.6
2.8
3.0
ns
3, 5
Notes:
1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OV
DD
.
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the
rising edge of the input L2SYNC_IN (see
Figure 8). Input timings are measured at the pins.
3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint
of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive
50-
load (see Figure 10).
4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous
BurstRAMs, L2CR[14–15] = 01 or 10 is recommended. For pipelined late write synchronous BurstRAMs,
L2CR[14–15] = 11 is recommended.
5. Guaranteed by design and characterization.
6. Revisions prior to Rev. 2.8 (Rev. E) were limited in performance and did not conform to this specification. For
more information, refer to Section 1.10.2, “Part Numbers Not Fully Addressed by This Document.”
Table 12. L2 Bus Interface AC Timing Specifications (continued)
At recommended operating conditions (see Table 3)
Parameter
Symbol
All Speed Grades
Unit
Notes
Min
Max
L2SYNC_IN
L2 Data and Data
Parity Inputs
VM
VM = Midpoint Voltage (L2OV
DD
/2)
t
DVL2CH
t
DXL2CH
t
L2CR
t
L2CF
L2SYNC_IN
All Outputs
VM
VM = Midpoint Voltage (L2OV
DD
/2)
t
L2CHOV
t
L2CHOX
VM
L2DATA BUS
t
L2CHOZ
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