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1394 OHCI Memory-Mapped Register Space
134
March 5 2007 June 2011
SCPS154C
8.9
Bus Options Register
The bus options register externally maps to the second quadlet of the Bus_Info_Block. See
Table 87 for a
complete description of the register contents.
OHCI register offset:
20h
Register type:
Read/Write, Read-only
Default value:
0000 A0X2h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
1
0
1
0
X
0
1
0
Table 87. Bus Options Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
irmc
RW
Isochronous resource-manager capable. IEEE 1394 bus-management field. Must be valid when
bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section
8.16)is set to 1b. The default value for this bit is 0b.
30
cmc
RW
Cycle master capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in
the host controller control register at OHCI offset 50h/54h (see Section
8.16) is set to 1b. The default
value for this bit is 0b.
29
isc
RW
Isochronous support capable. IEEE 1394 bus-management field. Must be valid when bit 17
(linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section
8.16) is set
to 1b. The default value for this bit is 0b.
28
bmc
RW
Bus manager capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in
the host controller control register at OHCI offset 50h/54h (see Section
8.16) is set to 1b. The default
value for this bit is 0b.
27
pmc
RW
Power-management capable. IEEE 1394 bus-management field. When bit 27 is set to 1b, this
indicates that the node is power-management capable. Must be valid when bit 17 (linkEnable) in the
host controller control register at OHCI offset 50h/54h (see Section
8.16) is set to 1b. The default
value for this bit is 0b.
2624
RSVD
R
Reserved. Bits 2624 return 000b when read.
2316
cyc_clk_acc
RW
Cycle master clock accuracy, in parts per million. IEEE 1394 bus-management field. Must be valid
when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see
Section
8.16) is set to 1b. The default value for this field is 00h.
1512
max_rec
RW
Maximum request. IEEE 1394 bus-management field. Hardware initializes this field to indicate the
maximum number of bytes in a block request packet that is supported by the implementation. This
value, max_rec_bytes, must be 512 or greater, and is calculated by 2^(max_rec + 1). Software may
change this field; however, this field must be valid at any time bit 17 (linkEnable) in the host controller
control register at OHCI offset 50h/54h (see Section
8.16) is set to 1b. A received block write request
packet with a length greater than max_rec_bytes may generate an ack_type_error. This field is not
affected by a software reset, and defaults to value indicating 2048 bytes on a system (hardware)
reset. The default value for this field is Ah.
118
RSVD
R
Reserved. Bits 118 return 0h when read.
76
g
RW
Generation counter. This field is incremented if any portion of the configuration ROM has been
incremented since the prior bus reset.
53
RSVD
R
Reserved. Bits 53 return 000b when read.
20
Lnk_spd
R
Link speed. This field returns 010b, indicating that the link speeds of 100M bits/s, 200M bits/s, and
400M bits/s are supported.
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Not Recommended for New Designs