參數(shù)資料
型號： XE8801AMI027LF
廠商： Semtech
文件頁數(shù)： 112/135頁
文件大小： 0K
描述： IC DAS 16BIT FLASH 8K MTP 44LQFP
標準包裝： 800
系列： XE880x
應用： 感測機
核心處理器： Coolrisc816?
程序存儲器類型： 閃存（22 kB）
控制器系列： XE8000
RAM 容量： 512 x 8
接口： UART，USRT
輸入/輸出數(shù)： 24
電源電壓： 2.4 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-VFQFN 裸露焊盤
包裝： 托盤
供應商設備封裝： 44-MLPQ（7x7）
產(chǎn)品目錄頁面： 585 (CN2011-ZH PDF)
配用： XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
Semtech 2005
www.semtech.com
14-6
XE8801A – SX8801R
14.6.3
Reception
On detection of the start bit, the UartRxBusy bit is set. On detection of the stop bit, the received data are
transferred from the internal shift register to the register RegUartRx. At the same time, the UartRxFull bit is set
and an interrupt is generated on Irq_uart_Rx. This indicates that new data is available in RegUartRx. The timing
diagram is shown in Figure 14-2.
The UartRxFull bit is cleared when RegUartRx is read. If the register was not read before the receiver transfers a
new word to it, the bit UartRxOErr (overflow error) is set and the previous contents of the register is lost.
UartRxOErr is cleared by writing any data to RegUartRxSta.
The bit UartRxSErr is set if a start error has been detected. The bit is updated at data transfer to RegUartRx.
The bit UartRxPErr is set if a parity error has been detected, i.e. the received parity bit is not equal to the
calculated parity of the received data. The bit is updated at data transfer to RegUartRx.
The bit UartRxFErr in RegUartRxSta shows that a frame error has been detected. No stop bit has been detected.
Asynchronous Reception
read of RegUartRx (software)
reguartrx_shift
word 1
RegUartRx
word 1
shift clock
Rx
start
b0
b6/7
parity
stop
UartRxBusy
UartRxFull
Irq_uart_Rx
Figure 14-2. Uart reception timing diagram.
14.7
Interrupt or polling
The transmission and reception software can be driven by interruption or by polling the status bits.
Interrupt driven reception: each time an Irq_uart_Rx interrupt is generated, a new word is available in RegUartRx.
The register has to be read before a new word is received.
Interrupt driven transmission: each time the contents of RegUartTx is transferred to the transmission shift register,
an Irq_uart_Tx interrupt is generated. A new word can then be written to RegUartTx.
Reception driven by polling: the UartRxFull bit is to be read and checked. When it is 1, the RegUartRx register
contains new data and has to be read before a new word is received.
Transmission driven by polling: the UartTxFull bit is to read and checked. When it is 0, the RegUartTx register is
empty and a new word can be written to it.
Not
Recommended
for
New
Designs
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