參數(shù)資料
型號： XE8801AMI000WP
廠商： Semtech
文件頁數(shù)： 69/135頁
文件大?。?/td> 0K
描述： SENSING MACHINE WITH 16 + 10 BIT
標(biāo)準(zhǔn)包裝： 558
系列： XE880x
應(yīng)用： 感測機
核心處理器： Coolrisc816?
程序存儲器類型： 閃存（22 kB）
控制器系列： XE8000
RAM 容量： 512 x 8
接口： UART，USRT
輸入/輸出數(shù)： 24
電源電壓： 2.4 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 模具
包裝： 托盤
配用： XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
其它名稱： Q2722595
Semtech 2005
www.semtech.com
6-5
XE8801A – SX8801R
The last bit concerns the sleep mode control (see system documentation for the sleep mode description).
when Sleep is set to 1, and SleepEn is 1, the sleep mode is entered. The bit always reads back a 0.
The RegSysCtrl register enables the different available reset sources and the sleep mode.
EnResWD enables the reset due to the watchdog (can not be disabled once enabled).
EnBusError enables the reset due to a bus error condition.
EnResPConf enables the reset of the port configurations when reset by Port A, a Bus Error or the
watchdog.
SleepEn unlocks the Sleep bit. As long as SleepEn is 0, the Sleep bit has no effect.
6.7
Watchdog
The watchdog is a timer which has to be cleared at least every 2 seconds by the software to prevent a reset being
generated by the timeout condition.
The watchdog can be enabled by software by setting the EnResWD bit in the RegSysCtrl register to 1. It can then
only be disabled by a power on reset.
The watchdog timer can be cleared by writing consecutively the values Hx0A and Hx03 to the RegSysWD register.
The sequence must strictly be respected to clear the watchdog.
In assembler code, the sequence to clear the watchdog is:
move AddrRegSysWD, #0x0A
move AddrRegSysWD, #0x03
Only writing Hx0A followed by Hx03 resets the WD. If some other write instruction is done to the RegSysWD
between the writing of the Hx0A and Hx03 values, the watchdog timer will not be cleared.
It is possible to read the status of the watchdog in the RegSysWD register. The watchdog is a 4 bit counter with a
count range between 0 and 7. The system reset is generated when the counter is reaching the value 8.
6.8
Start-up and watchdog specifications
At start-up of the circuit, the POR (power-on-reset) block generates a reset signal during tPOR. The circuit starts
software execution after this period (see system chapter). The POR is intended to force the circuit in a correct state
at start-up. For precise monitoring of the supply voltage, the voltage level detector (VLD) has to be used.
Not
Recommended
for
New
Designs
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