參數(shù)資料
型號(hào): XE3005I064TRLF
廠商: Semtech
文件頁數(shù): 5/37頁
文件大?。?/td> 0K
描述: IC CODEC LOW PWR 16BIT 20-UCSP
標(biāo)準(zhǔn)包裝: 1
類型: 音頻編解碼器
數(shù)據(jù)接口: 串行
分辨率(位): 16 b
ADC / DAC 數(shù)量: 1 / 1
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 78 / 78
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 78 / 78
電壓 - 電源,模擬: 1.8 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.8 V ~ 3.6 V
工作溫度: -20°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-UCSP?
供應(yīng)商設(shè)備封裝: 20-UCSP?(5x4)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: XE3005I064DKR
Semtech 2005
www.semtech.com
13
XE3005/XE3006
3
SERIAL COMMUNICATIONS
3.1
SERIAL AUDIO INTERFACE
The Serial Audio Interface is a 4-wire interface for bi-directional communication of audio data. The 4 terminals are listed
below:
BCLK:
Bit serial clock, one clock cycle corresponds to one data bit transmitted or received.
FSYNC:
Frame Synchronization. This signal indicates the start of a data word. The frequency of the FSYNC
corresponds to the sample frequency of the CODEC.
SDI:
Serial Data In, data received from external device and sent to DAC.
SDO:
Serial Data Out, data received from ADC and sent to external device.
The same clock (BCLK) and synchronization (FSYNC) signals are used for both sending and receiving. The
synchronization signal FSYNC must have a fixed ratio with the master clock signal MCLK.
The Serial Audio Interface supports two formats that are commonly used for audio/voice CODECs and that are referred to
as SFS (Short Frame Synchronization) and LFS (Long Frame Synchronization). Data can be transmitted and received in
2 channels. Which channel is selected depends on the programmed values in the registers. The two interface protocols
are shown below.
FSYNC
SDO
SDI
BCLK
msb
lsb
msb
channel 1, sample n
channel 2, no data
channel 1, sample n+1
n15
n14
n0
n+115
n15
n14
n0
n+115
-
Figure 13: Audio interface timing LFS mode, channel 1
FSYNC
BCLK
channel 1, sample n
channel 2, sample n
channel 1, sample n+1
SDO
SDI
msb
lsb
msb
n15
n14
n0
n+115
n15
n14
n0
n+115
-
Figure 14: Audio interface timing in SFS mode, channel 1
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