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參數(shù)資料
| 型號： | XE3005I064TRLF |
| 廠商： | Semtech |
| 文件頁數(shù)： | 6/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC LOW PWR 16BIT 20-UCSP |
| 標準包裝： | 1 |
| 類型： | 音頻編解碼器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 16 b |
| ADC / DAC 數(shù)量： | 1 / 1 |
| 三角積分調(diào)變： | 是 |
| S/N 比，標準 ADC / DAC (db)： | 78 / 78 |
| 動態(tài)范圍，標準 ADC / DAC (db)： | 78 / 78 |
| 電壓 - 電源，模擬： | 1.8 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 1.8 V ~ 3.6 V |
| 工作溫度： | -20°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-UCSP? |
| 供應商設備封裝： | 20-UCSP?（5x4） |
| 包裝： | 標準包裝 |
| 其它名稱： | XE3005I064DKR |
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Semtech 2005
www.semtech.com
14
XE3005/XE3006
SDI Data should be changed on the rising edge of BCLK. The SDI data will be read by the CODEC on the falling edge of
BLCK. SDO data will change on the rising edge of the BCLK. The SDO data should be read on the falling edge of the
BLCK. Each rising edge of the FSYNC indicates the start of a new sample.
3.1.1
LFS Optimization
For transmitting and receiving, 32 clock cycles in one frame are always required (figure 12 and 13). This is even the case
when only 16 bits have to be sent or received. In most cases this can be handled easily with a DSP and microcontroller.
If the user wants to send a minimum of BLCK cycles, it is possible to shorten channel 1 (channel 2 can not be shortened).
In the LFS mode the possibility exists to shorten the number of BLCK cycles to 17 instead of 32. In this case the data is
transmitted and received in channel 2. Channel 1 is shortened to one BLCK cycle only.
Note! This optimization is possible in slave mode only.
The figure 15 shows this special LFS mode.
Figure 15: Audio interface timing in LFS mode, 17 BLCK cycles, channel 2
3.2
REGISTER PROGRAMMING
The control registers define the configuration of the CODEC and define the various modes of operation. During power-up,
all registers will be configured with default values. The control register set consists of 16 registers. A detailed description
is provided chapter 7.
The control registers can be changed in the two following ways:
1.
Logic values at SPI pins during power-up
There are 3 bits inside the registers which are configured depending on the logic values of the pins SS, SCK and MOSI
during the power up startup sequence as described in section 2.1.10
Value at power up
Influenced bits of registers
comments
SS = 1
SS = 0
Register I(0)=0
Register I(0)=1
MCLKDIV division by 1
MCLKDIV division by 2
SCK = 0
SCK = 1
Register J(0)=1
Register J(0)=0
SFS protocol
LFS protocol
MOSI = 0
MOSI = 1
Register E(2) = 0
Register E(2) = 1
preamplifier gain x5
preamplifier gain x20
FSYNC
SDO
SDI
BCLK
msb
lsb
channel 1, no data
channel 2, sample n
n15
n14
n0
n15
n14
n0
-
msb
channel 2, sample n+1
n15
n14
n15
n14
-
channel 1, no data
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