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參數(shù)資料
| 型號(hào)： | XE3005I033TRLF |
| 廠商： | Semtech |
| 文件頁數(shù)： | 36/37頁 |
| 文件大小： | 0K |
| 描述： | IC CODEC LOW PWR 16BIT 20-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 音頻編解碼器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 16 b |
| ADC / DAC 數(shù)量： | 1 / 1 |
| 三角積分調(diào)變： | 是 |
| S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： | 78 / 78 |
| 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 78 / 78 |
| 電壓 - 電源，模擬： | 1.8 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 1.8 V ~ 3.6 V |
| 工作溫度： | -20°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 585 (CN2011-ZH PDF) |
| 其它名稱： | XE3005I033DKR |
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Semtech 2005
www.semtech.com
8
XE3005/XE3006
2.1.4
Digital Loop Back
In digital loop back mode, the ADC output is routed directly to the DAC input. This allows in-circuit system level tests. The
digital loop back mode can be selected through register J.
2.1.5
Operating Frequency
A master clock (MCLK) has to be applied to the XE3005/3006. The clock frequency of the signal applied to the MCLK pin
may vary between 1.024 MHz minimum and 33.9 MHz maximum. The maximum internal clock signal frequency
(MCLK/div_factor) should not exceed 12.288 MHz.
The div_factor can be set by the user in register I to 1,2 or 4. The default value for div_factor is ‘1’.
2.1.6
Serial Audio Interface
The Serial Audio Interface is a 4-wire interface for bi-directional communication of audio data. It operates on the bit serial
clock BCLK and the frame synchronization signal FSYNC. The sampling frequency of the CODEC corresponds to the
rate at which the Audio Serial Interface will put out succeeding frames. One frame always corresponds to one sample.
One frame always contains 2 channels.
Synchronizing the Serial Audio Interface to the MCLK is recommended. FSYNC and MCLK must have a fixed ratio as
defined by the following relation:
FSYNC = Sampling frequency = frame rate = MCLK/(256 x div_factor).
The pin BCLK defines the time when the data must be presented to the serial audio interface and shifted into (pin SDI) or
out of (pin SDO) the CODEC. The number of BCLK periods in one FSYNC period is 32. The user can select to use the
first 16 clock cycles (channel 1) or the second 16 clock cycles (channel 2) of BLCK to shift in or out the data samples.
The table below shows some examples of the relationships between MCLK, BCLK and FSYNC
MCLK
Div_factor
BCLK
FSYNC
2048 kHz
1
256 kHz
8 kHz
8192 kHz
4
256 kHz
8 kHz
5120 kHz
1
640 kHz
20 kHz
22579.2 kHz
2
1411.2 kHz
44.1 kHz
The table below shows the possible functional configurations of the serial audio interface
CODEC
supported protocol
master
LFS (Long Frame Sync)
slave
LFS, LFS Optimization and SFS (Short Frame Sync)
By default the Serial Audio Interface operates in slave, SFS mode. In slave mode the user needs to generate the signals
BLCK, FSYNC and supply to the CODEC.
In master mode the CODEC generates the BLCK and FSYNC signals. In that case the BLCK operates at 32 times the
frequency of FSYNC. The CODEC master mode can be used with the LFS protocol only.
The register J is used for the different setups of the serial audio interface.
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| XE3005I064TRLF | 功能描述:IC CODEC LOW PWR 16BIT 20-UCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
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