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參數(shù)資料
| 型號： | XCS40XL-5CS280C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 57/83頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 3.3V C-TEMP 280-CSBGA |
| 標準包裝： | 119 |
| 系列： | Spartan®-XL |
| LAB/CLB數(shù)： | 784 |
| 邏輯元件/單元數(shù)： | 1862 |
| RAM 位總計： | 25088 |
| 輸入/輸出數(shù)： | 224 |
| 門數(shù)： | 40000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 280-TFBGA，CSPBGA |
| 供應商設(shè)備封裝： | 280-CSBGA（16x16） |
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Spartan and Spartan-XL FPGA Families Data Sheet
60
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
Spartan-XL Family IOB Input Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. These path delays, provided as a
guideline, have been extracted from the static timing ana-
lyzer report. All timing parameters assume worst-case oper-
ating conditions (supply voltage and junction temperature).
Symbol
Device
Speed Grade
Units
-5
-4
Description
Min
Max
Min
Max
Setup Times
TECIK
Clock Enable (EC) to Clock (IK)
All devices
0.0
-
0.0
-
ns
TPICK
Pad to Clock (IK), no delay
All devices
1.0
-
1.2
-
ns
TPOCK
Pad to Fast Capture Latch Enable (OK), no delay
All devices
0.7
-
0.8
-
ns
Hold Times
All Hold Times
All devices
0.0
-
0.0
-
ns
Propagation Delays
TPID
Pad to I1, I2
All devices
-
0.9
-
1.1
ns
TPLI
Pad to I1, I2 via transparent input latch, no delay
All devices
-
2.1
-
2.5
ns
TIKRI
Clock (IK) to I1, I2 (flip-flop)
All devices
-
1.0
-
1.1
ns
TIKLI
Clock (IK) to I1, I2 (latch enable, active Low)
All devices
-
1.1
-
1.2
ns
Delay Adder for Input with Full Delay Option
TDelay
TPICKD = TPICK + TDelay
TPDLI = TPLI + TDelay
XCS05XL
4.0
-
4.7
-
ns
XCS10XL
4.8
-
5.6
-
ns
XCS20XL
5.0
-
5.9
-
ns
XCS30XL
5.5
-
6.5
-
ns
XCS40XL
6.5
-
7.6
-
ns
Global Set/Reset
TMRW
Minimum GSR pulse width
All devices
10.5
-
11.5
-
ns
TRRI
Delay from GSR input to any Q
XCS05XL
-
9.0
-
10.5
ns
XCS10XL
-
9.5
-
11.0
ns
XCS20XL
-
10.0
-
11.5
ns
XCS30XL
-
11.0
-
12.5
ns
XCS40XL
-
12.0
-
13.5
ns
Notes:
1.
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.
2.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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|---|---|
| XCS40XL-5CS280I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
| XCS40XL-5CS84C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS40XL-5CS84I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS40XL-5PC100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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