參數(shù)資料
型號(hào): XCS40XL-5CS280C
廠商: Xilinx Inc
文件頁數(shù): 26/83頁
文件大?。?/td> 0K
描述: IC FPGA 3.3V C-TEMP 280-CSBGA
標(biāo)準(zhǔn)包裝: 119
系列: Spartan®-XL
LAB/CLB數(shù): 784
邏輯元件/單元數(shù): 1862
RAM 位總計(jì): 25088
輸入/輸出數(shù): 224
門數(shù): 40000
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 280-TFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 280-CSBGA(16x16)
Spartan and Spartan-XL FPGA Families Data Sheet
32
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
Legend:
A selection of CRC or non-CRC error checking is allowed by
the bitstream generation software. The Spartan-XL family
Express mode only supports non-CRC error checking. The
non-CRC
error
checking
tests
for
a
designated
end-of-frame field for each frame. For CRC error checking,
the software calculates a running CRC and inserts a unique
four-bit partial check at the end of each frame. The 11-bit
CRC check of the last frame of an FPGA includes the last
seven data bits.
Detection of an error results in the suspension of data load-
ing before DONE goes High, and the pulling down of the
INIT pin. In Master serial mode, CCLK continues to operate
externally. The user must detect INIT and initialize a new
configuration by pulsing the PROGRAM pin Low or cycling
VCC.
Cyclic Redundancy Check (CRC) for Configura-
tion and Readback
The Cyclic Redundancy Check is a method of error detec-
tion in data transmission applications. Generally, the trans-
mitting system performs a calculation on the serial
bitstream. The result of this calculation is tagged onto the
data stream as additional check bits. The receiving system
performs an identical calculation on the bitstream and com-
pares the result with the received checksum.
Each data frame of the configuration bitstream has four
error bits at the end, as shown in Table 16. If a frame data
error is detected during the loading of the FPGA, the config-
uration process with a potentially corrupted bitstream is ter-
minated. The FPGA pulls the INIT pin Low and goes into a
Wait state.
Table 16: Spartan/XL Data Stream Formats
Data Type
Serial Modes
(D0...)
Express Mode
(D0-D7)
(Spartan-XL only)
Fill Byte
11111111b
FFFFh
Preamble Code
0010b
11110010b
Length Count
COUNT[23:0]
COUNT[23:0](1)
Fill Bits
1111b
-
Field Check
Code
-
11010010b
Start Field
0b
11111110b(2)
Data Frame
DATA[n–1:0]
CRC or Constant
Field Check
xxxx (CRC)
or 0110b
11010010b
Extend Write
Cycle
-
FFD2FFFFFFh
Postamble
01111111b
-
Start-Up Bytes(3)
FFh
FFFFFFFFFFFFFFh
Unshaded
Once per bitstream
Light
Once per data frame
Dark
Once per device
Notes:
1.
Not used by configuration logic.
2.
11111111b for XCS40XL only.
3.
Development system may add more start-up bytes.
相關(guān)PDF資料
PDF描述
IDT70V28L15PF IC SRAM 1MBIT 15NS 100TQFP
KMPC866TVR133A IC MPU POWERQUICC 133MHZ 357PBGA
IDT70V09L15PF IC SRAM 1MBIT 15NS 100TQFP
IDT7038L20PFI IC SRAM 1.125MBIT 20NS 100TQFP
IDT7038L15PF IC SRAM 1.125MBIT 15NS 100TQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCS40XL-5CS280I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA
XCS40XL-5CS84C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS40XL-5CS84I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS40XL-5PC100C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS40XL-5PC100I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays