參數(shù)資料
型號(hào)： XCS30-3PQ240C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 55/83頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 5V C-TEMP 240-PQFP
產(chǎn)品變化通告： Spartan,Virtex FPGA/SCD Discontinuation 18/Oct/2010
標(biāo)準(zhǔn)包裝： 24
系列： Spartan®
LAB/CLB數(shù)： 576
邏輯元件/單元數(shù)： 1368
RAM 位總計(jì)： 18432
輸入/輸出數(shù)： 192
門(mén)數(shù)： 30000
電源電壓： 4.75 V ~ 5.25 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 240-BFQFP
供應(yīng)商設(shè)備封裝： 240-PQFP（32x32）
Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
59
Product Specification
R
Product Obsolete/Under Obsolescence
Spartan-XL Family Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Pin-to-pin timing
parameters are derived from measuring external and inter-
nal test patterns and are guaranteed over worst-case oper-
ating conditions (supply voltage and junction temperature).
Listed below are representative values for typical pin loca-
tions and normal clock loading.
Spartan-XL Family Setup and Hold
Capacitive Load Factor
Figure 35 shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the specified
output delay if the load capacitance is different than 50 pF.
For example, if the actual load capacitance is 120 pF, add
2.5 ns to the specified delay. If the load capacitance is 20
pF, subtract 0.8 ns from the specified output delay.
Figure 35 is usable over the specified operating conditions
of voltage and temperature and is independent of the output
slew rate control.
Symbol
Description
Device
Speed Grade
Units
-5
-4
Max
Input Setup/Hold Times Using Global Clock and IFF
TSUF/THF
No Delay
XCS05XL
1.1/2.0
1.6/2.6
ns
XCS10XL
1.0/2.2
1.5/2.8
ns
XCS20XL
0.9/2.4
1.4/3.0
ns
XCS30XL
0.8/2.6
1.3/3.2
ns
XCS40XL
0.7/2.8
1.2/3.4
ns
TSU/TH
Full Delay
XCS05XL
3.9/0.0
5.1/0.0
ns
XCS10XL
4.1/0.0
5.3/0.0
ns
XCS20XL
4.3/0.0
5.5/0.0
ns
XCS30XL
4.5/0.0
5.7/0.0
ns
XCS40XL
4.7/0.0
5.9/0.0
ns
Notes:
1.
IFF = Input Flip-Flop or Latch
2.
Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a
reference load of one clock pin per IOB/CLB.
Figure 35: Delay Factor at Various Capacitive Loads
DS060_35_080400
-2
0
20
406080
Capacitance (pF)
Delta
Dela
y
(ns)
100
120
140
-1
0
1
2
3
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