參數(shù)資料
型號(hào)： XCS10XL-5CS144C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 16/83頁(yè)
文件大小： 0K
描述： IC FPGA 3.3V C-TEMP 144-CSBGA
標(biāo)準(zhǔn)包裝： 198
系列： Spartan®-XL
LAB/CLB數(shù)： 196
邏輯元件/單元數(shù)： 466
RAM 位總計(jì)： 6272
輸入/輸出數(shù)： 112
門數(shù)： 10000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 144-TFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 144-LCSBGA（12x12）
Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
23
Product Specification
R
Product Obsolete/Under Obsolescence
Bit Sequence
The bit sequence within each IOB is: In, Out, 3-state. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins contributes
all three bits.
The first two bits in the I/O data register are TDO.T and
TDO.O, which can be used for the capture of internal sig-
nals. The final bit is BSCANT.UPD, which can be used to
drive an internal net. These locations are primarily used by
Xilinx for internal testing.
From a cavity-up view of the chip (as shown in the FPGA
Editor), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in Figure 21.
The device-specific pinout tables for the Spartan/XL devices
include the boundary scan locations for each IOB pin.
BSDL (Boundary Scan Description Language) files for
Spartan/XL devices are available on the Xilinx website in
the File Download area. Note that the 5V Spartan devices
and 3V Spartan-XL devices have different BSDL files.
Including Boundary Scan in a Design
If boundary scan is only to be used during configuration, no
special elements need be included in the schematic or HDL
code. In this case, the special boundary scan pins TDI,
TMS, TCK and TDO can be used for user functions after
configuration.
To indicate that boundary scan remain enabled after config-
uration, place the BSCAN library symbol and connect the
TDI, TMS, TCK and TDO pad symbols to the appropriate
pins, as shown in Figure 22.
Table 12: Boundary Scan Instructions
Instruction
Test
Selected
TDO
Source
I/O Data
Source
I2
I1
I0
0
EXTEST
DR
0
1
SAMPLE/
PRELOAD
DR
Pin/Logic
0
1
0
USER 1
BSCAN.
TDO1
User Logic
0
1
USER 2
BSCAN.
TDO2
User Logic
1
0
READBACK
Readback
Data
Pin/Logic
1
0
1
CONFIGURE
DOUT
Disabled
110
IDCODE
(Spartan-XL
only)
IDCODE
Register
-
1
BYPASS
Bypass
Register
-
Figure 21: Boundary Scan Bit Sequence
Figure 22: Boundary Scan Example
Bit 0 ( TDO end)
Bit 1
Bit 2
TDO.T
TDO.O
Top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
MODE.I
Bottom-edge IOBs (Left to Right)
Right-edge IOBs (Bottom to Top)
BSCANT.UPD
(TDI end)
DS060_21_080400
TDI
TMS
TCK
TDO1
TDO2
TDO
DRCK
IDLE
SEL1
SEL2
TDI
TMS
TCK
TDO
BSCAN
To User
Logic
IBUF
Optional
From
User Logic
To User
Logic
DS060_22_080400
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