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參數(shù)資料
| 型號(hào)： | XCR3512XL |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XCR3512XL: 512 Macrocell CPLD |
| 中文描述： | XCR3512XL：512宏單元CPLD |
| 文件頁(yè)數(shù)： | 3/14頁(yè) |
| 文件大?。?/td> | 108K |
| 代理商： | XCR3512XL |
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XCR3512XL: 512 Macrocell CPLD
DS081 (v1.2) September 4, 2001
Advance Product Specification
1-800-255-77783
R
AC Electrical Characteristics Over Recommended Operating Conditions
(1,2)
Figure 2:
Typical I/V Curve for the XPLA3 Family
Symbol
T
PD1
T
PD2
T
CO
T
SUF(4)
T
SU(4)
T
H(4)
T
WLH(4)
Tt
PLH(4)
T
R(4)
T
L(4)
f
SYSTEM(4)
T
CONFIG(4)
T
INIT(4)
T
POE(4)
T
POD(4)
T
PCO(4)
T
PAO(4)
Notes:
1.
Specifications measured with one output switching.
2.
See XPLA3 family data sheet (DS012) for recommended operating conditions.
3.
See
Figure 4
for derating.
4.
These parameters guaranteed by design and/or characterization, not testing.
5.
Typical current draw during configuration is 12 mA at 3.6V.
6.
Output C
L
= 5 pF.
Parameter
-7
-10
-12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
μ
s
μ
s
ns
ns
ns
ns
Min.
Max.
Min.
-
-
-
3.5
6.5
0
4.0
6.0
-
-
-
-
-
-
-
-
-
Max.
9.0
10.0
5.8
-
-
-
-
-
20
20
97
TBD
TBD
11.0
11.0
10.3
11.0
Min.
-
-
-
3.5
7.9
0
5.0
7.5
-
-
-
-
-
-
-
-
-
Max.
10.8
12.0
6.9
-
-
-
-
-
20
20
77
TBD
TBD
13.0
13.0
12.4
13.0
Propagation delay time (single p-term)
Propagation delay time (OR array)
(3)
Clock to output (global synchronous pin clock)
Setup time fast
Setup time
Hold time
Global Clock pulse width (High or Low)
P-term clock pulse width
Input rise time
Input fall time
Maximum system frequency
Configuration time
(5)
ISP initialization time
P-term OE to output enabled
P-term OE to output disabled
(6)
P-term clock to output
P-term set/reset to output valid
0
0
10
20
30
40
50
60
70
80
90
100
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Volts
I
OL
(3.3V)
I
OH
(3.3V)
I
OH
(2.7V)
m
DS012_10_041901
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