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參數(shù)資料
| 型號： | XCR3512XL |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XCR3512XL: 512 Macrocell CPLD |
| 中文描述： | XCR3512XL：512宏單元CPLD |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 108K |
| 代理商： | XCR3512XL |
DS081 (v1.2) September 4, 2001
Advance Product Specification
1-800-255-77781
2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
Lowest power 512 macrocell CPLD
7.5 ns pin-to-pin logic delays
System frequencies up to 127 MHz
512 macrocells with 12,800 usable gates
Available in small footprint packages
-
208-pin PQFP (180 user I/O)
-
256-ball FBGA (212 user I/O)
-
324-ball FBGA (260 user I/O)
Optimized for 3.3V systems
-
Ultra low power operation
-
5V tolerant I/O pins with 3.3V core supply
-
Advanced 0.35 micron five layer metal EEPROM
process
-
FZP CMOS design technology
Advanced system features
-
In-system programming
-
Input registers
-
Predictable timing model
-
Up to 23 clocks available per function block
-
Excellent pin retention during design changes
-
Full IEEE Standard 1149.1 boundary-scan (JTAG)
-
Four global clocks
-
Eight product term control terms per function block
Fast ISP programming times
Port Enable pin for additional I/O
2.7V to 3.6V supply voltage at industrial grade voltage
range
Programmable slew rate control per output
Security bit prevents unauthorized access
Refer to XPLA3 family data sheet (DS012) for
architecture description
Description
The XCR3512XL is a 3.3V, 512 macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of 32 function blocks provide
12,800 usable gates. Pin-to-pin propagation delays are
7.5 ns with a maximum system frequency of 127 MHz.
TotalCMOS Design Technique for
Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1
and
Table 1
showing the I
CC
vs. Frequency of our
XCR3512XL TotalCMOS CPLD (data taken with 32
up/down, loadable 16-bit counters at 3.3V, 25
°
C).
0
XCR3512XL: 512 Macrocell CPLD
DS081 (v1.2) September 4, 2001
0
14
Advance Product Specification
R
Figure 1:
XCR3512XL Typical I
CC
vs. Frequency at V
CC
= 3.3V, 25
°
C
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120
140
160
DS024_01_112700
Frequency (MHz)
T
Table 1:
Typical I
CC
vs. Frequency at V
CC
= 3.3V, 25
°
C
Frequency (MHz)
0
1
10
20
40
60
80
100
120
140
Typical I
CC
(mA)
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相關PDF資料 |
PDF描述 |
|---|---|
| XCR3512XL-10FG324C | XCR3512XL: 512 Macrocell CPLD |
| XCR3512XL-10FG324I | XCR3512XL: 512 Macrocell CPLD |
| XCR3512XL-10FT256C | XCR3512XL: 512 Macrocell CPLD |
| XCR3512XL-10FT256I | XCR3512XL: 512 Macrocell CPLD |
| XCR3512XL-10PQ208C | XCR3512XL: 512 Macrocell CPLD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3512XL-10FG324C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 12K GATES 512 MCRCLLS 125MHZ 0.35UM 3. - Trays |
| XCR3512XL-10FG324I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 12K GATES 512 MCRCLLS 125MHZ 0.35UM 3. - Trays |
| XCR3512XL-10FGG324C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 12K GATES 512 MCRCLLS 125MHZ 0.35UM 3. - Trays |
| XCR3512XL-10FGG324I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 12K GATES 512 MCRCLLS 125MHZ 0.35UM 3. - Trays |
| XCR3512XL-10FT256C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 12K GATES 512 MCRCLLS 125MHZ COMM 0.35 - Trays |
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