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參數(shù)資料
| 型號(hào)： | XCR3064XL-7CP56I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ISP CPLD 64 MCELL 3.3V 56-CSP |
| 標(biāo)準(zhǔn)包裝： | 360 |
| 系列： | CoolRunner XPLA3 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 1K 次編程/擦除循環(huán)） |
| 最大延遲時(shí)間 tpd(1)： | 7.0ns |
| 電壓電源 - 內(nèi)部： | 2.7 V ~ 3.6 V |
| 邏輯元件/邏輯塊數(shù)目： | 4 |
| 宏單元數(shù)： | 64 |
| 門數(shù)： | 1500 |
| 輸入/輸出數(shù)： | 48 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 56-CSBGA（6x6） |
| 包裝： | 托盤 |
CoolRunner XPLA3 CPLD
DS012 (v2.5) May 26, 2009
Product Specification
R
mented in the buried macrocell can be fed back to the ZIA
via the macrocell feedback path.
If a macrocell pin is configured as a registered input, there is
a direct path to the register to provide a fast input setup
time. If the macrocell is configured as a latch, the register
clock input functions as the latch enable, with the latch
transparent when this signal is High. The hardwired clock
enable is non-functional when the macrocell is configured
as a latch.
I/O Cell
The OE (Output Enable) multiplexer has eight possible
modes (Figure 6). When the I/O Cell is configured as an
input (or 3-stated output), a half latch feature exists. This
half latch pulls the input High (through a weak pull-up) if the
input should float and cross the threshold. This protects the
input from staying in the linear region and causing an
increased amount of power consumption. This same weak
pull-up can be enabled in software such that it is always on
when the I/O Cell is configured as an input. This weak pull
up is automatically turned on when a pin is unused by the
design.
The I/O Cell is 5V tolerant when the device is powered.
Each output has independent slew rate control (fast or slow)
which assists in reducing EMI emissions.
See individual device data sheets for 3.3V PCI electrical
specification compatibility.
Note that an I/O macrocell used as buried logic that does
not have the I/O pin used for input is considered to be
unused, and the weak pull-up resistors will be turned on. It
is recommended that any unused I/O pins on the CoolRun-
ner XPLA3 family of CPLDs be left unconnected. Dedicated
input pins (CLKx/INx) do not have on-chip weak pull-up
resistors; therefore unused dedicated input pins must have
external termination. As with all CMOS devices, do not
allow inputs to float.
Figure 5: XPLA3 Macrocell Architecture
Global CLK
Universal CLK
P-term CLK
CT [4:7]
ds012_05_122299
Universal PST
CT [0:5]
Universal RST
CT [0:5]
To ZIA
To I/O
PAD
Note: Global CLK signals come from pins.
To ZIA
VFM
RST
PST
D/T/L
CLKEn
Q
CT4
P-term
48
PLA OR Term
From PT Array
1
Figure 6: I/O Cell
GND (Weak P.U.)
VCC
Universal OE
CT
GND
OE [2:0]
To Macrocell / ZIA
From Macrocell
I/O Pin
WP
Slew
Control
OE
Decode
0
1
2
3
4
5
6
7
I/O Pin
State
3-State
Function CT0
Function CT1
Function CT2
Function CT6
Universal OE
Enable
Weak P.U.
ds012_06_121699
Weak Pull-up
OE = 7
VCC
3
4
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| XCR3064XL-7CP56I0770 | 制造商:Xilinx 功能描述: |
| XCR3064XL-7CPG56C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 1.5K GATES 64 MCRCLLS 166.67MHZ 0.35UM - Trays |
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| XCR3064XL-7CS48C | 功能描述:IC ISP CPLD 64 MCELL 3.3V 48-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner XPLA3 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| XCR3064XL-7CS48I | 功能描述:IC ISP CPLD 64 MCELL 3.3V 48-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner XPLA3 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
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