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參數(shù)資料
| 型號(hào)： | XCR3064XL-7CP56I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ISP CPLD 64 MCELL 3.3V 56-CSP |
| 標(biāo)準(zhǔn)包裝： | 360 |
| 系列： | CoolRunner XPLA3 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 1K 次編程/擦除循環(huán)） |
| 最大延遲時(shí)間 tpd(1)： | 7.0ns |
| 電壓電源 - 內(nèi)部： | 2.7 V ~ 3.6 V |
| 邏輯元件/邏輯塊數(shù)目： | 4 |
| 宏單元數(shù)： | 64 |
| 門數(shù)： | 1500 |
| 輸入/輸出數(shù)： | 48 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 56-CSBGA（6x6） |
| 包裝： | 托盤 |
CoolRunner XPLA3 CPLD
4
DS012 (v2.5) May 26, 2009
Product Specification
R
Macrocell Architecture
Figure 5 shows the architecture of the macrocell used in the
CoolRunner XPLA3 CPLD. Any macrocell can be reset or
preset on power-up. Each macrocell register can be config-
ured as a D-, T-, or Latch-type flip-flop, or bypassed if the
macrocell is required as a combinatorial logic function.
Each of these flip-flops can be clocked from any one of eight
sources or their complements. There are two global syn-
chronous clocks that are selected from the four external
clock pins. There is one universal clock signal. The clock
input signals CT[4:7] (Local Control Terms) can be individu-
ally configured as either a PRODUCT term or SUM term
equation created from the 40 signals available inside the
function block.
There are two muxed paths to the ZIA. One mux selects
from either the output of the VFM or the output of the regis-
ter. The other mux selects from the output of the register or
from the I/O pad of the macrocell. When the I/O pin is used
as an output, the output buffer is enabled, and the macrocell
feedback path can be used to feed back the logic imple-
mented in the macrocell. When an I/O pin is used as an
input, the output buffer is 3-stated and the input signal is fed
into the ZIA via the I/O feedback path. The logic imple-
Figure 3: Xilinx CoolRunner XPLA3 Function Block Architecture
Figure 4: Variable Function Multiplexer
Foldback NAND
(PT[8:15])
(PT[0:47])
(PT0)
(PT7)
(PT[32:47])
(PT16)
(PT[0:47])
(PT31)
To Local Control Term (LCT0)
To Universal Control Term (UCT) Mux
To Local Control Term (LCT7)
P-term Clocks
8
Product
Term
Array
40 x 48
ZIA
40
VFM
Macrocell 1
D
Q
I/O1
ZIA
1
48
D
Q
ZIA
I/O16
VFM
Macrocell 16
1
48
DS012_02_101200
From PLA OR Term
To Combinatorial Path
and Register Input
From P-term
DS012_03_121699
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3064XL-7CP56I0770 | 制造商:Xilinx 功能描述: |
| XCR3064XL-7CPG56C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 1.5K GATES 64 MCRCLLS 166.67MHZ 0.35UM - Trays |
| XCR3064XL-7CPG56I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 1.5K GATES 64 MCRCLLS 166.67MHZ 0.35UM - Trays |
| XCR3064XL-7CS48C | 功能描述:IC ISP CPLD 64 MCELL 3.3V 48-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner XPLA3 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| XCR3064XL-7CS48I | 功能描述:IC ISP CPLD 64 MCELL 3.3V 48-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner XPLA3 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
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