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參數資料
| 型號： | XCF32PVOG48 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Platform Flash In-System Programmable Configuration PROMS |
| 中文描述： | 平臺Flash在系統(tǒng)可編程配置方案管理系統(tǒng) |
| 文件頁數： | 22/46頁 |
| 文件大小： | 525K |
| 代理商： | XCF32PVOG48 |
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Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.9) May 09, 2006
www.xilinx.com
22
R
Reset and Power-On Reset Activation
At power up, the device requires the V
CCINT
power supply to
monotonically rise to the nominal operating voltage within
the specified V
CCINT
rise time. If the power supply cannot
meet this requirement, then the device might not perform
power-on reset properly. During the power-up sequence,
OE/RESET is held Low by the PROM. Once the required
supplies have reached their respective POR (Power On
Reset) thresholds, the OE/RESET release is delayed (T
OER
minimum) to allow more margin for the power supplies to
stabilize before initiating configuration. The OE/RESET pin
is connected to an external 4.7k
Ω
pull-up resistor and also
to the target FPGA's INIT pin. For systems utilizing
slow-rising power supplies, an additional power monitoring
circuit can be used to delay the target configuration until the
system power reaches minimum operating voltages by
holding the OE/RESET pin Low. When OE/RESET is
released, the FPGA’s INIT pin is pulled High allowing the
FPGA's configuration sequence to begin. If the power drops
below the power-down threshold (V
CCPD
), the PROM resets
and OE/RESET is again held Low until the after the POR
threshold is reached. OE/RESET polarity is not
programmable. These power-up requirements are shown
graphically in
Figure 14, page 22
.
For a fully powered Platform Flash PROM, a reset occurs
whenever OE/RESET is asserted (Low) or CE is
deasserted (High). The address counter is reset, CEO is
driven High, and the remaining outputs are placed in a
high-impedance state.
Notes:
1.
The XCFxxS PROM only requires V
CCINT
to rise above
its POR threshold before releasing OE/RESET.
The XCFxxP PROM requires both V
CCINT
to rise above
its POR threshold and for V
CCO
to reach the
recommended operating voltage level before releasing
OE/RESET.
2.
I/O Input Voltage Tolerance and Power Sequencing
The I/Os on each re-programmable Platform Flash PROM
are fully 3.3V-tolerant. This allows 3V CMOS signals to
connect directly to the inputs without damage. The core
power supply (V
CCINT
), JTAG pin power supply (V
CCJ
),
output power supply (V
CCO
), and external 3V CMOS I/O
signals can be applied in any order.
Additionally, for the XCFxxS PROM only, when V
CCO
is
supplied at 2.5V or 3.3V and V
CCINT
is supplied at 3.3V, the
I/Os are 5V-tolerant. This allows 5V CMOS signals to connect
directly to the inputs on a powered XCFxxS PROM without
damage. Failure to power the PROM correctly while supplying
a 5V input signal may result in damage to the XCFxxS device.
Standby Mode
The PROM enters a low-power standby mode whenever CE
is deasserted (High). In standby mode, the address counter
is reset, CEO is driven High, and the remaining outputs are
placed in a high-impedance state regardless of the state of
the OE/RESET input. For the device to remain in the
low-power standby mode, the JTAG pins TMS, TDI, and
TDO must not be pulled Low, and TCK must be stopped
(High or Low).
When using the FPGA DONE signal to drive the PROM CE
pin High to reduce standby power after configuration, an
external pull-up resistor should be used. Typically a 330
Ω
Figure 14:
Platform Flash PROM Power-Up Requirements
T
OER
V
CCINT
V
CCPOR
V
CCPD
200 μ
s
r
a
mp
50 m
s
r
a
mp
T
OER
T
R
S
T
TIME (m
s
)
A
s
low-r
a
mping V
CCINT
su
pply m
a
y
s
till
b
e
b
elow the minim
u
m oper
a
ting
volt
a
ge when OE/RE
S
ET i
s
rele
as
ed.
In thi
s
c
as
e, the config
u
r
a
tion
s
e
qu
ence m
us
t
b
e del
a
yed
u
ntil
b
oth
V
CCINT
a
nd V
CCO
h
a
ve re
a
ched their
recommended oper
a
ting condition
s
.
Recommended Operatin
g
Ran
g
e
Delay or Re
s
tart
Confi
g
uration
d
s
12
3
_21_10
3
10
3
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