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參數(shù)資料
| 型號： | XC95288-10HQ208C |
| 英文描述： | Flash Complex PLD |
| 中文描述： | 閃光復(fù)雜可編程邏輯器件 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 133K |
| 代理商： | XC95288-10HQ208C |
R
September 15, 1999 (Version 5.0)
11
XC9500 In-System Programmable CPLD Family
5
Each output has independent slew rate control. Output
edge rates may be slowed down to reduce system noise
(with an additional time delay of t
SLEW
) through program-
ming. See
Figure 11
.
Each IOB provides user programmable ground pin capabil-
ity. This allows device I/O pins to be configured as addi-
tional ground pins. By tying strategically located
programmable ground pins to the external ground connec-
tion, system noise generated from large numbers of simul-
taneous switching outputs may be reduced.
A control pull-up resistor (typically 10K ohms) is attached to
each device I/O pin to prevent them from floating when the
device is not in normal user operation. This resistor is
active during device programming mode and system
power-up. It is also activated for an erased device. The
resistor is deactivated during normal operation.
The output driver is capable of supplying 24 mA output
drive. All output drivers in the device may be configured for
either 5 V TTL levels or 3.3 V levels by connecting the
device output voltage supply (V
CCIO
) to a 5 V or 3.3 V
voltage supply.
Figure 12
shows how the XC9500 device
can be used in 5 V only and mixed 3.3 V/5 V systems.
Pin-Locking Capability
The capability to lock the user defined pin assignments dur-
ing design changes depends on the ability of the architec-
ture to adapt to unexpected changes. The XC9500 devices
have architectural features that enhance the ability to
accept design changes while maintaining the same pinout.
The XC9500 architecture provides maximum routing within
the FastCONNECT switch matrix, and incorporates a flexi-
ble Function Block that allows block-wide allocation of
available product terms. This provides a high level of confi-
dence of maintaining both input and output pin assign-
ments for unexpected design changes.
For extensive design changes requiring higher logic capac-
ity than is available in the initially chosen device, the new
design may be able to fit into a larger pin-compatible device
using the same pin assignments. The same board may be
used with a higher density device without the expense of
board rework.
Time
0
0
1.5 V
Standard
Output
Voltage
(a)
Slew-Rated Limited
t
SLEW
Time
1.5 V
Output
Voltage
(b)
t
SLEW
Standard
Slew-Rated Limited
X5900
Figure 11: Output Slew-Rate For (a) Rising and (b) Falling Outputs
Figure 12: XC9500 Devices in (a) 5 V Systems and (b) Mixed 3.3 V/5 V Systems
IN
OUT
CPLD
V
CCINT
V
CCIO
5 V
5 V CMOS
5 V
or
or
0 V
3.3 V
GND
(b)
X5901
5 V TTL
3.6 V
0 V
3.3 V
3.3 V
0 V
3.3 V
3.3 V
0 V
IN
OUT
CPLD
V
CCINT
V
CCIO
5 V
5 V CMOS
5 V
or
or
0 V
GND
(a)
5 V TTL
3.6 V
0 V
3.3 V
3.3 V
0 V
5 V TTL
~ 4 V
0 V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC95288-10HQ208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC95288 In-System Programmable CPLD |
| XC95288-15BG352C | 功能描述:IC CPLD 288 MCELL C-TEMP 352-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500 標準包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC95288-15BG352I | 功能描述:IC CPLD 288 MCELL I-TEMP 352-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500 標準包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC95288-15BGG352C | 制造商:Xilinx 功能描述:XILINX XC95288-15BGG352C CPLD - Trays 制造商:Xilinx 功能描述:Xilinx XC95288-15BGG352C CPLD |
| XC95288-15BGG352I | 制造商:Xilinx 功能描述:XILINX XC95288-15BGG352I CPLD - Trays 制造商:Xilinx 功能描述:Xilinx XC95288-15BGG352I CPLD |
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