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參數(shù)資料
| 型號(hào)： | XC7336-5 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 36-Macrocell CMOS EPLD |
| 中文描述： | 36宏單元的CMOS可編程邏輯器件 |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 117K |
| 代理商： | XC7336-5 |
2-3
Figure 2. Fast Function Block and Macrocell Schematic for the XC7318, XC7336, and XC73144
Figure 3. Fast Function Block and Macrocell Schematic for the XC7354, XC7372, and XC73108
I/O Pin
OE Control
Sum-of-Products to
Succeeding Macrocell
5
Q
D/T
S/R
Fast
Clocks
0 1
1 of 9 Macrocells
Feedback
to UIM
24
Inputs from
UIM
AND Array
5 Private
P-Terms per
Macrocell
X5725
Sum-of-Products
from
Previous
Macrocell
P-Term
AControl
12 from Fast
Input Pins
12
9
9 from FFB
Macrocell
Feedback
3
0
1
TControl
Output
Polarity
2 Global
Fast OE
2
Pin Feedback
to UIM
Input-Pad
Register/Latch
(optional)
(XC73144 only)
I
OL
= 24 mA
Pin
OE Control
Sum-of-Products to
Succeeding Macrocell
5
Q
D
S
Fast
Clocks
0 1
1 of 9 Macrocells
Feedback
to UIM
24
Inputs from
UIM
AND Array
5 Private
P-Terms per
Macrocell
X5761
Sum-of-Products
from
Previous
Macrocell
P-Term
AControl
12 from Fast
Input Pins
12
9
9 from FFB
Macrocell
Feedback
3
0
1
TRegister
Control
2 Global
Fast OE
2
Pin Feedback
to UIM
(XC7354 Only)
Input-Pad
Register/Latch
(optional)
(XC7354 only)
I
OL
= 24 mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC7336-7 | 36-Macrocell CMOS EPLD |
| XC7354 | XC7300 CMOS EPLD Family |
| XC7372 | XC7300 CMOS EPLD Family |
| XC74WL74AASR | CMOS Logic D-Type Flip Flop |
| XC9500 | XC9500 In-System Programmable CPLD Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC73365PQ44C | 制造商: 功能描述: 制造商:undefined 功能描述: |
| XC7336-7 | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:36-Macrocell CMOS EPLD |
| XC7336PC44ACK | 制造商:Xilinx 功能描述: |
| XC7336PC44ACK15C | 制造商:Xilinx 功能描述:New Factory Tubes (26 per tube) |
| XC7354 | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:XC7300 CMOS EPLD Family |
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