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參數(shù)資料
| 型號： | XC7336-5 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 36-Macrocell CMOS EPLD |
| 中文描述： | 36宏單元的CMOS可編程邏輯器件 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 117K |
| 代理商： | XC7336-5 |
2-1
Features
High-performance Erasable Programmable Logic
Devices (EPLDs)
– 5 / 7.5 ns pin-to-pin speeds on all fast inputs
– Up to 167 MHz maximum clock frequency
Advanced Dual-Block architecture
– Fast Function Blocks
– High-Density Function Blocks
(XC7354, XC7372, XC73108, XC73144)
100% interconnect matrix
High-speed arithmetic carry network
– 1 ns ripple-carry delay per bit
– 43 to 61 MHz 18-bit accumulators
Multiple independent clocks
Each input programmable as direct, latched, or
registered
High-drive 24 mA output
I/O operation at 3.3 V or 5 V
Meets JEDEC Standard (8-1A) for 3.3 V
±
0.3 V
Power management options
Multiple security bits for design protection
Supported by industry standard design and verification
tools
100% PCI compliant
Description
The XC7300 family employs a unique Dual-Block architec-
ture, which provides high speed operations via Fast Func-
tion Blocks and/or high density capability via High Density
Function Blocks.
Fast Function Blocks (FFBs) provide fast, pin-to-pin
speed and logic throughput for critical decoding and ultra-
fast state machine applications. High-Density Function
Blocks (FBs) provide maximum logic density and system-
level features to implement complex functions with pre-
dictable timing for adders and accumulators, wide func-
tions and state machines requiring large numbers of
product terms, and other forms of complex logic.
In addition, the XC7300 architecture employs the Univer-
sal Interconnect Matrix (UIM) which guarantees 100%
interconnect of all internal functions. This interconnect
scheme provides constant, short interconnect delays for
all routing paths through the UIM. Constant interconnect
delays simplify device timing and guarantee design perfor-
mance, regardless of logic placement within the chip.
All XC7300 devices are designed in 0.8
technology.
μ
CMOS EPROM
All XC7300 EPLDs include programmable power manage-
ment features to specify high-performance or low-power
operation on an individual Macrocell-by-Macrocell basis.
Unused Macrocells are automatically turned off to mini-
XC7300 CMOS EPLD Family
Product Description
XC7318
XC7336
XC7354
XC7372
XC73108
XC73144
Typical 22V10 Equivalent
Number of Macrocells
Number of Function Blocks
Number of Flip-Flops
Number of Fast Inputs
Number of Signal Pins
1.5 – 2
18
2
18
12
38
3 – 4
36
4
36
12
38
6
8
12
108
12
198
12
120
16
144
16
276
12
156
54
6
108
12
58
72
8
126
12
84
The XC7300 Family
This document was created with FrameMaker 4 0 2
相關PDF資料 |
PDF描述 |
|---|---|
| XC7336-7 | 36-Macrocell CMOS EPLD |
| XC7354 | XC7300 CMOS EPLD Family |
| XC7372 | XC7300 CMOS EPLD Family |
| XC74WL74AASR | CMOS Logic D-Type Flip Flop |
| XC9500 | XC9500 In-System Programmable CPLD Family |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC73365PQ44C | 制造商: 功能描述: 制造商:undefined 功能描述: |
| XC7336-7 | 制造商:XILINX 制造商全稱:XILINX 功能描述:36-Macrocell CMOS EPLD |
| XC7336PC44ACK | 制造商:Xilinx 功能描述: |
| XC7336PC44ACK15C | 制造商:Xilinx 功能描述:New Factory Tubes (26 per tube) |
| XC7354 | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC7300 CMOS EPLD Family |
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