T
參數(shù)資料
型號: XC6SLX25T-3FG484I
廠商: Xilinx Inc
文件頁數(shù): 81/89頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 6 484FGGBGA
標(biāo)準(zhǔn)包裝: 60
系列: Spartan® 6 LXT
LAB/CLB數(shù): 1879
邏輯元件/單元數(shù): 24051
RAM 位總計: 958464
輸入/輸出數(shù): 250
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-BBGA
供應(yīng)商設(shè)備封裝: 484-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
82
TPKGSKEW
Package Skew(1)
LX45
CSG324
70
ps
CS(G)484
99
ps
FG(G)484
109
ps
FG(G)676
138
ps
LX45T
CSG324
75
ps
CS(G)484
100
ps
FG(G)484
95
ps
LX75
CS(G)484
101
ps
FG(G)484
107
ps
FG(G)676
161
ps
LX75T
CS(G)484
107
ps
FG(G)484
110
ps
FG(G)676
134
ps
LX100
CS(G)484
95
ps
FG(G)484
155
ps
FG(G)676
144
ps
LX100T
CS(G)484
88
ps
FG(G)484
111
ps
FG(G)676
147
ps
FG(G)900
134
ps
LX150
CS(G)484
84
ps
FG(G)484
103
ps
FG(G)676
115
ps
FG(G)900
121
ps
LX150T
CS(G)484
83
ps
FG(G)484
88
ps
FG(G)676
141
ps
FG(G)900
120
ps
Notes:
1.
These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from Pad to Ball.
2.
Some of the devices are available in both Pb and Pb-free (additional G) packages as standard ordering options. See DS160: Spartan-6 Family
Overview for more information.
Table 80: Sample Window
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
TSAMP
Sampling Error at Receiver Pins(2)
All
510
530
740
ps
TSAMP_BUFIO2
Sampling Error at Receiver Pins using
BUFIO2(3)
All
430
450
590
ps
Notes:
1.
LXT devices are not available with a -1L speed grade.
2.
This parameter indicates the total sampling error of Spartan-6 FPGA DDR input registers, measured across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 DCM jitter
- DCM accuracy (phase offset)
- DCM phase shift resolution
These measurements do not include package or clock tree skew.
3.
This parameter indicates the total sampling error of Spartan-6 FPGA DDR input registers, measured across voltage, temperature, and process. The
characterization methodology uses the BUFIO2 clock network and IODELAY2 to capture the DDR input registers’ edges of operation. These
measurements do not include package or clock tree skew.
Table 79: Package Skew (Cont’d)
Symbol
Description
Device
Package(2)
Value
Units
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