參數(shù)資料
型號(hào)： XC6SLX150T-2FG900I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 10/89頁(yè)
文件大?。?/td> 0K
描述： IC FPGA SPARTAN 6 900FGGBGA
標(biāo)準(zhǔn)包裝： 27
系列： Spartan® 6 LXT
LAB/CLB數(shù)： 11519
邏輯元件/單元數(shù)： 147443
RAM 位總計(jì)： 4939776
輸入/輸出數(shù)： 540
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 900-BBGA
供應(yīng)商設(shè)備封裝： 900-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
18
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in
Spartan-6 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values
are subject to the same guidelines as the Switching Characteristics, page 19.
Table 25: Interface Performances
Description
I/O Resource
Clock
Buffer
Data
Width
Speed Grade
Units
-3
-3N
-2
-1L
Networking Applications(1)
SDR LVDS transmitter or receiver
IOB SDR register
BUFG
–
400
375
250
Mb/s
DDR LVDS transmitter or receiver
ODDR2/IDDR2 register
2 BUFGs
–
800
750
500
Mb/s
SDR LVDS transmitter
OSERDES2
BUFPLL
2
500
250
Mb/s
3
750
375
Mb/s
4-8
1080
1050
950
500
Mb/s
DDR LVDS transmitter
OSERDES2
2 BUFIO2s
2
500
250
Mb/s
3
750
375
Mb/s
4-8
1080
1050
950
500
Mb/s
SDR LVDS receiver
ISERDES2 in RETIMED mode
BUFPLL
2
500
—
Mb/s
3
750
—
Mb/s
4-8
1080
1050
950
—
Mb/s
DDR LVDS receiver
ISERDES2 in RETIMED mode
2 BUFIO2s
2
500
—
Mb/s
3
750
—
Mb/s
4-8
1080
1050
950
—
Mb/s
Memory Interfaces (Implemented using the Spartan-6 FPGA Memory Controller Block)(2)
Standard Performance (Standard VCCINT)
DDR
400
400
350
Mb/s
DDR2
667
625
400
Mb/s
DDR3
800
667
—
Mb/s
LPDDR (Mobile_DDR)
400
400
350
Mb/s
Extended Performance (Requires Extended Performance VCCINT)(3)
DDR2
800
667
—
Mb/s
Notes:
1.
Refer to XAPP1064, Source-Synchronous Serialization and Deserialization (up to 1050 Mb/s) and UG381, Spartan-6 FPGA SelectIO
Resources User Guide.
2.
Refer to UG388, Spartan-6 FPGA Memory Controller User Guide.
3.
Extended Memory Controller block performance for DDR2 can be achieved using the extended performance VCCINT range from Table 2.
4.
The LX4 device, all devices in the TQG144 and CPG196 packages, and the -3N speed grade do not support a Memory Controller Block.
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