參數(shù)資料
型號(hào): XC56L307VF160
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 39/104頁(yè)
文件大?。?/td> 0K
描述: IC DSP 24BIT FIXED POINT 196-BGA
標(biāo)準(zhǔn)包裝: 126
系列: DSP563xx
類(lèi)型: 定點(diǎn)
接口: 主機(jī)接口,SSI,SCI
時(shí)鐘速率: 160MHz
非易失內(nèi)存: ROM(576 B)
芯片上RAM: 576kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 196-LBGA
供應(yīng)商設(shè)備封裝: 196-MAPBGA(15x15)
包裝: 托盤(pán)
DSP56L307 Technical Data, Rev. 6
iv
Freescale Semiconductor
Target Applications
Wireless and wireline infrastructure applications
Multi-channel wireless local loop systems
DSP resource boards
High-speed modem banks
Packet telephony
Product Documentation
The documents listed in Table 2 are required for a complete description of the DSP56L307 device and are
necessary to design properly with the part. Documentation is available from a local Freescale distributor, a
Freescale semiconductor sales office, or a Freescale Semiconductor Literature Distribution Center. For
documentation updates, visit the Freescale DSP website. See the contact information on the back cover of this
document.
External Memory
Expansion
Data memory expansion to two 256 K
× 24-bit word memory spaces using the standard external address
lines
Program memory expansion to one 256 K
× 24-bit words memory space using the standard external
address lines
External memory expansion port
Chip select logic for glueless interface to static random access memory (SRAMs)
Internal DRAM Controller for glueless interface to dynamic random access memory (DRAMs) up to 100
MHz operating frequency
Power Dissipation
Very low-power CMOS design
Wait and Stop low-power standby modes
Fully static design specified to operate down to 0 Hz (dc)
Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-
dependent)
Packaging
Molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions.
Table 2. DSP56L307 Documentation
Name
Description
Order Number
DSP56L307
User’s Manual
Detailed functional description of the DSP56L307 memory configuration,
operation, and register programming
DSP56L307UM
DSP56300 Family
Manual
Detailed description of the DSP56300 family processor core and instruction set
DSP56300FM
Application Notes
Documents describing specific applications or optimized device operation
including code examples
See the DSP56L307 product website
Table 1. DSP56L307 Features (Continued)
Feature
Description
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