
DSP56309 Product Brief, Rev. 1
2
Freescale Semiconductor
Features
Table 1 lists the features of the DSP56309 device.
 Table 1. DSP56309 Features
Feature
Description
High-Performance
DSP56300 Core
 100 million multiply-accumulates per second (MMACS) with a 100 MHz clock at 3.3 V nominal
 Data arithmetic logic unit (Data ALU) with fully pipelined 24
× 24-bit parallel multiplier-accumulator (MAC),
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional
ALU instructions, and 24-bit or 16-bit arithmetic support under software control
 Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for
DSP applications (including immediate offsets), internal instruction cache controller, internal memory-
expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
 Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-
and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and
triggering from interrupt lines and all peripherals
 Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock
with skew elimination
 Hardware debugging support including on-chip emulation (OnCE) module, Joint Test Action Group (JTAG)
test access port (TAP)
Internal Peripherals
 Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides
glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
 Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows
six-channel home theater)
 Serial communications interface (SCI) with baud rate generator
 Triple timer module
 Up to thirty-four programmable general-purpose input/output (GPIO) pins, depending on which peripherals
are enabled
Internal Memories
192
× 24-bit bootstrap ROM
8 K
× 24-bit RAM total
 Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:
External Memory
Expansion
 Data memory expansion to two 256 K
× 24-bit word memory spaces using the standard external address
lines
 Program memory expansion to one 256 K
× 24-bit words memory space using the standard external
address lines
 External memory expansion port
 Chip select logic for glueless interface to static random access memory (SRAMs)
 Internal DRAM Controller for glueless interface to dynamic random access memory (DRAMs)
Power Dissipation
 Very low-power CMOS design
 Wait and Stop low-power standby modes
 Fully static design specified to operate down to 0 Hz (dc)
 Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-
dependent)
Packaging
 144-pin TQFP package in lead-free or lead-bearing versions
 196-pin molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions
Program RAM
Size
Instruction
Cache Size
X Data RAM
Size
Y Data RAM
Size
Instruction
Cache
Switch Mode
20480
× 24 bits
0
7168
× 24 bits
7168
× 24 bits
disabled
19456
× 24 bits
1024
× 24-bit
7168
× 24 bits
7168
× 24 bits
enabled
disabled
24576
× 24 bits
0
5120
× 24 bits
5120
× 24 bits
disabled
enabled
23552
× 24 bits
1024
× 24-bit
5120
× 24 bits
5120
× 24 bits
enabled