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| 型號(hào)： | XC56309AG100AR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT 100MHZ 144-LQFP |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 系列： | DSP563xx |
| 類型： | 定點(diǎn) |
| 接口： | 主機(jī)接口，SSI，SCI |
| 時(shí)鐘速率： | 100MHz |
| 非易失內(nèi)存： | ROM（576 B） |
| 芯片上RAM： | 24kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP（20x20） |
| 包裝： | 帶卷 (TR) |
Freescale Semiconductor
Product Brief Advance Information
DSP56309PB
Rev. 1, 2/2005
Freescale Semiconductor, Inc., 1996, 2005. All rights reserved.
DSP56309
24-Bit Digital Signal Processor
The DSP56309 is a member of the DSP56300 core family of programmable CMOS DSPs. The DSP56300 core
includes a barrel shifter, 24-bit addressing, an instruction cache, and direct memory access (DMA). The DSP56309
offers 100 million multiply-accumulates per second (MMACS) at 3.0–3.6 V using an internal 100 MHz clock. The
large internal memory is ideal for wireless infrastructure and wireless local-loop applications. The DSP56300 core
family offers a new level of performance in speed and power provided by its rich instruction set and low-power
dissipation, thus enabling a new generation of wireless, multimedia, and telecommunications products.
Figure 1. DSP56309 Block Diagram
PLL
OnCE
Clock
Generator
Internal
Data
Bus
Switch
YAB
XAB
PAB
YDB
XDB
PDB
GDB
MODB/IRQB
MODC/IRQC
External
Data Bus
Switch
13
MODD/IRQD
DSP56300
6
16
24-Bit
24
18
DDB
DAB
Peripheral
Core
YM
_
E
B
XM
_
E
B
PM
_
E
B
PI
O
_
E
B
Expansion Area
6
JTAG
5
3
RESET
MODA/IRQA
PINIT/NMI
2
Bootstrap
ROM
EXTAL
XTAL
Address
Control
Data
Address
Generation
Unit
Six-Channel
DMA Unit
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
Data ALU
24
× 24 + 56 →56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
Power
Management
External
Bus
Interface
and Inst.
Cache
Control
External
Address
Bus
Switch
Memory Expansion Area
DE
X Data
RAM
7168
× 24
bits
(default)
Y Data
RAM
7168
× 24
bits
(default)
Triple
Timer
HI08
ESSI
SCI
PrograM
20480
× 24
bits
(default)
RAM
The DSP56309 is intended
for applications benefiting
from a large amount of
internal memory, such as
wireless infrastructure
applications.
Note: This document contains information on a new product. Specifications and information herein are subject to change without notice.
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