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參數(shù)資料
| 型號： | XC5202-5PQ100C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 24/73頁 |
| 文件大小： | 0K |
| 描述： | IC - FPGA SPEED GRADE 5 COM TEMP |
| 產(chǎn)品變化通告： | XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010 |
| 標準包裝： | 66 |
| 系列： | XC5200 |
| LAB/CLB數(shù)： | 64 |
| 邏輯元件/單元數(shù)： | 256 |
| 輸入/輸出數(shù)： | 81 |
| 門數(shù)： | 3000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 100-BQFP |
| 供應商設備封裝： | 100-QFP（14x20） |
| 其它名稱： | Q858790 XC5202-5PQ1000C XC5202-5PQ1000C-ND |
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R
XC5200 Series Field Programmable Gate Arrays
7-112
November 5, 1998 (Version 5.2)
DONE High to active user I/O is controlled by an option to
the bitstream generation software.
Release of Global Reset After DONE Goes High
By default, Global Reset (GR) is released two CCLK cycles
after the DONE pin goes High. If CCLK is not clocked twice
after DONE goes High, all flip-flops are held in their initial
reset state. The delay from DONE High to GR inactive is
controlled by an option to the bitstream generation soft-
ware.
Configuration Complete After DONE Goes High
Three full CCLK cycles are required after the DONE pin
goes High, as shown in Figure 25 on page 109. If CCLK is
not clocked three times after DONE goes High, readback
cannot be initiated and most boundary scan instructions
cannot be used.
Configuration Through the Boundary Scan
Pins
XC5200-Series devices can be configured through the
boundary scan pins.
For detailed information, refer to the Xilinx application note
XAPP017, “
Boundary Scan in XC4000 and XC5200
Devices.”
Readback
The user can read back the content of configuration mem-
ory and the level of certain internal nodes without interfer-
ing with the normal operation of the device.
Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs.
DONE
*
**
QS
R
1
0
1
0
1
0
1
0
1
GR ENABLE
GR INVERT
STARTUP.GR
STARTUP.GTS
GTS INVERT
GTS ENABLE
CONTROLLED BY STARTUP SYMBOL
IN THE USER SCHEMATIC (SEE
LIBRARIES GUIDE)
GLOBAL RESET OF
ALL CLB FLIP-FLOPS/LATCHES
IOBs OPERATIONAL PER CONFIGURATION
GLOBAL 3-STATE OF ALL IOBs
Q2
Q3
Q1/Q4
DONE
IN
STARTUP
Q0
Q1
Q2
Q3
Q4
M
" FINISHED "
ENABLES BOUNDARY
SCAN, READBACK AND
CONTROLS THE OSCILLATOR
K
SQ
K
DQ
K
DQ
K
DQ
K
DQ
FULL
LENGTH COUNT
CLEAR MEMORY
CCLK
STARTUP.CLK
USER NET
CONFIGURATION BIT OPTIONS SELECTED BY USER
X9002
Figure 26: Start-up Logic
Product Obsolete or Under Obsolescence
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相關代理商/技術參數(shù) |
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|---|---|
| XC5202-5PQ100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC5202-5PQ160C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XC5202-5PQ208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XC5202-5PQ240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
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