參數(shù)資料
型號: XC4VLX100-10FFG1148C
廠商: Xilinx Inc
文件頁數(shù): 41/58頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-4 100K 1148-FBGA
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-4 LX
LAB/CLB數(shù): 12288
邏輯元件/單元數(shù): 110592
RAM 位總計: 4423680
輸入/輸出數(shù): 768
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1148-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1148-FCPBGA(35x35)
其它名稱: 122-1486
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
46
Virtex-4 FPGA Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 56. Values are expressed in nanoseconds unless otherwise noted.
Table 56: Global Clock Setup and Hold for LVCMOS25 Standard, with DCM
Symbol
Description
Device
Speed Grade
Units
-12
-11
-10
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSDCM / TPHDCM
No Delay Global Clock and IFF(2) with DCM
XC4VLX15
1.35
–0.72
1.52
–0.67
1.54
–0.62
ns
XC4VLX25
1.28
–0.58
1.50
–0.57
1.58
–0.55
ns
XC4VLX40
1.25
–0.55
1.44
–0.50
1.50
–0.46
ns
XC4VLX60
1.25
–0.43
1.47
–0.40
1.55
–0.36
ns
XC4VLX80
1.22
–0.26
1.42
–0.21
1.49
–0.15
ns
XC4VLX100
1.27
–0.20
1.48
–0.14
1.56
–0.08
ns
XC4VLX160
1.54
–0.20
1.79
–0.13
1.89
–0.05
ns
XC4VLX200
N/A
1.90
0.03
2.00
0.15
ns
XC4VSX25
1.25
–0.50
1.47
–0.48
1.55
–0.48
ns
XC4VSX35
1.21
–0.41
1.43
–0.38
1.50
–0.34
ns
XC4VSX55
1.25
–0.23
1.47
–0.18
1.55
–0.13
ns
XC4VFX12
1.35
–0.71
1.55
–0.69
1.61
–0.69
ns
XC4VFX20
1.25
–0.52
1.48
–0.51
1.56
–0.51
ns
XC4VFX40
1.23
–0.18
1.45
–0.13
1.52
–0.08
ns
XC4VFX60
1.17
–0.06
1.37
0.01
1.44
0.09
ns
XC4VFX100
1.21
0.11
1.42
0.20
1.49
0.31
ns
XC4VFX140
N/A
1.68
0.21
1.76
0.31
ns
Notes:
1.
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the
Global Clock input signal with the slowest route and heaviest load.
2.
These measurements include:
CLK0 DCM jitter
IFF = Input Flip-Flop or Latch
3.
Use IBIS to determine any duty-cycle distortion incurred using various standards.
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