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參數(shù)資料
| 型號(hào)： | XC4062XL-09HQ240C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 15/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA C-TEMP 3.3V 240-HQFP |
| 產(chǎn)品變化通告： | Product Discontinuation 19/Feb/2007 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 2304 |
| 邏輯元件/單元數(shù)： | 5472 |
| RAM 位總計(jì)： | 73728 |
| 輸入/輸出數(shù)： | 193 |
| 門(mén)數(shù)： | 62000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 240-BFQFP 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 240-PQFP（32x32） |
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R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-80
DS005 (v2.0) March 1, 2013 - Product Specification
Product Obsolete/Under Obsolescence
XC4000XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
Output Flip-Flop, Clock to Out
Capacitive Load Factor
Figure 1 shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the speci-
fied output delay if the load capacitance is different than
50 pF. For example, if the actual load capacitance is
120 pF, add 2.5 ns to the specified delay. If the load capac-
itance is 20 pF, subtract 0.8 ns from the specified output
delay.
Figure 1 is usable over the specified operating conditions of
voltage and temperature and is independent of the output
slew rate control.
Figure 1: Delay Factor at Various Capacitive Loads
Speed Grade
All
-3
-2
-1
-09
-08
Units
Description
Symbol
Device
Min
Max
Global Low Skew Clock to Output us-
ing Output Flip Flop
TICKOF
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
1.2
1.3
1.4
1.5
1.6
1.8
2.0
2.1
2.2
2.3
2.5
7.1
7.7
8.2
8.6
9.0
9.4
9.8
10.3
10.7
11.3
12.2
6.1
6.6
7.1
7.4
7.8
8.1
8.5
8.9
9.3
9.7
10.5
5.4
5.8
6.2
6.5
6.8
7.1
7.4
7.8
8.3
8.5
9.5
5.1
5.4
5.8
6.1
6.4
6.7
7.0
7.4
7.9
8.1
9.0
5.6
6.4
7.3
ns
For output SLOW option add
TSLOW
All Devices
0.5
3.0
2.5
2.0
1.7
1.6
ns
Notes:
Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin
clock-to-out delay for clocked outputs for FAST mode configurations.
Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 1.
X8257
-2
0
20
406080
Capacitance (pF)
Delta
Dela
y
(ns)
100
120
140
-1
0
1
2
3
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