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參數(shù)資料
| 型號： | XC3SD1800A-5FGG676C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 2/7頁 |
| 文件大小： | 0K |
| 描述： | SPARTAN-3ADSP FPGA 1800K 676FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標準包裝： | 40 |
| 系列： | Spartan®-3A DSP |
| LAB/CLB數(shù)： | 4160 |
| 邏輯元件/單元數(shù)： | 37440 |
| RAM 位總計： | 1548288 |
| 輸入/輸出數(shù)： | 519 |
| 門數(shù)： | 1800000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-FBGA（27x27） |
| 配用： | 122-1574-ND - KIT DEVELOPMENT SPARTAN 3ADSP |
Extended Spartan-3A Family Overview
DS706 (v1.1) February 2, 2011
Product Specification
2
R
Extended Spartan-3A Family Features
This section describes the features of the Extended Spartan-3A family of FPGAs.
Very low-cost, high-performance logic solution for high-
volume, cost-conscious applications
Use fewer standard components
Increase system reliability
Flexible power management
Low 1.2V core voltage
Selectable I/O voltage with 3.3V, 2.5V, 1.8V, 1.5V,
and 1.2V signaling
Full 3.3V ±10% compatibility and hot swap
compliance
Dual-range auxiliary voltage allows 3.3V setting to
simplify 3.3V-only design
Suspend and hibernate modes reduce system power
Leading connectivity platform
Multi-standard SelectIO interface pins support
most popular and emerging signaling standards
Up to 519 I/O pins or 227 differential signal pairs
LVCMOS, LVTTL, HSTL, SSTL single-ended I/O
Selectable output drive, up to 24 mA per pin
QUIETIO standard reduces I/O switching noise
640+ Mb/s data transfer rate per differential I/O
LVDS, RSDS, mini-LVDS, HSTL/SSTL differential
I/O with integrated differential termination resistors
Enhanced Double Data Rate (DDR) support
Compliant to 32-/64-bit, 33/66 MHz PCI technology
Abundant, flexible logic resources
Densities up to 53,712 logic cells, including
optional shift register or distributed RAM support
Efficient wide multiplexers and wide logic improve
performance and density
Fast look-ahead carry logic
IEEE 1149.1/1532 JTAG programming/debug port
Dedicated resources for high-speed digital signal
processing applications
18-bit by 18-bit multiplier with optional pipeline
250 MHz XtremeDSP DSP48A block in the
largest two devices
-
48-bit accumulator for multiply-accumulate
(MAC) operation
-
Integrated 18-bit pre-adder for multiply or
multiply-add operation
-
Optional cascaded Multiply or MAC
-
Fills the DSP performance gap between DSP
processors and high-end custom solutions
Precise clock management with up to eight Digital
Clock Managers (DCMs)
Clock skew elimination (delay locked loop)
Frequency synthesis, multiplication, division
High-resolution phase shifting
Wide frequency range (5 MHz to over 320 MHz)
Integrated flash memory in Spartan-3AN devices
Up to 16 Mb of internal flash for configuration and
application storage
Up to 11 Mb of user storage available for
embedded processing, code shadowing, or
scratchpad memory
Enables single-chip board designs for space-
conscious applications
Enhanced design security with flash memory
protection and security register
Eight low-skew global clock networks, eight additional
clocks per half device, plus abundant low-skew routing
Hierarchical SelectRAM memory architecture
Up to 2.2 Mb of fast block RAM with byte write
enables for processor applications
Up to 373 Kb of efficient distributed RAM
External DDR/DDR2 SDRAM support up to
400 Mb/s
Configuration interface to industry-standard PROMs
Low-cost, space-saving SPI serial flash PROM
x8 or x8/x16 parallel NOR flash PROM
Low-cost Xilinx Platform Flash with JTAG
Load multiple bitstreams under FPGA control with
MultiBoot capability
system software support
Industry’s most comprehensive IP library
MicroBlaze and PicoBlaze embedded processors
Integrate soft processor into FPGA to reduce Bill of
Materials
Reduce obsolescence risks with soft processors
Low-cost QFP and BGA packaging, Pb-free options
Common footprints support easy density migration
Low-cost starter kits from Xilinx, distributors, and third
parties
Complete starter kits designed for cost-sensitive,
high-volume applications with design examples
XA versions available for Automotive applications
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3SD3400A-4CS484C | 功能描述:SPARTAN-3ADSP FPGA 3400K 484CSA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3A DSP 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC3SD3400A-4CS484CES | 制造商:Xilinx 功能描述: |
| XC3SD3400A-4CS484I | 制造商:Xilinx 功能描述:FPGA SPARTAN-3A 3.4M GATES 53712 CELLS 667MHZ 1.2V 484PIN LC - Trays 制造商:Xilinx 功能描述:SPARTAN-3ADSP FPGA 3400K 484CSA 制造商:Xilinx 功能描述:IC FPGA 309 I/O 484CSPBGA |
| XC3SD3400A-4CSG484C | 功能描述:SPARTAN-3ADSP FPGA 3400K 484CSA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3A DSP 標準包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計:221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241 |
| XC3SD3400A-4CSG484I | 功能描述:IC FPGA SPARTAN-3A DSP 484-CSBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3A DSP 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
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