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參數(shù)資料
型號: XC3S50A-4VQ100I
廠商: Xilinx Inc
文件頁數(shù): 52/132頁
文件大小: 0K
描述: IC FPGA SPARTAN 3 100VQFP
標準包裝: 90
系列: Spartan®-3A
LAB/CLB數(shù): 176
邏輯元件/單元數(shù): 1584
RAM 位總計: 55296
輸入/輸出數(shù): 68
門數(shù): 50000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 100-TQFP
供應商設備封裝: 100-VQFP(14x14)
DC and Switching Characteristics
26
DS529-3 (v2.0) August 19, 2010
TIOICKPD
Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. The Input Delay is
programmed.
LVCMOS25(3)
1
XC3S400A
–1.12
ns
2
–1.70
ns
3
–2.08
ns
4
–2.38
ns
5
–2.23
ns
6
–2.69
ns
7
–3.08
ns
8
–3.35
ns
1
XC3S700A
–1.67
ns
2
–2.27
ns
3
–2.59
ns
4
–2.92
ns
5
–2.89
ns
6
–3.22
ns
7
–3.52
ns
8
–3.81
ns
1
XC3S1400A
–1.60
ns
2
–2.06
ns
3
–2.46
ns
4
–2.86
ns
5
–2.88
ns
6
–3.24
ns
7
–3.55
ns
8
–3.89
ns
Set/Reset Pulse Width
TRPW_IOB
Minimum pulse width to SR control
input on IOB
-
All
1.33
1.61
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
2.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 23.
3.
These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 23. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
Table 21: Sample Window (Source Synchronous)
Symbol
Description
Max
Units
TSAMP
Setup and hold
capture window of
an IOB flip-flop.
The input capture sample window value is highly specific to a particular application, device,
package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the
appropriate Xilinx Answer Record for application-specific values.
Answer Record 30879
ps
Table 20: Setup and Hold Times for the IOB Input Path(Continued)
Symbol
Description
Conditions
IFD_
DELAY_
VALUE
Device
Speed Grade
Units
-5
-4
Min
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