參數(shù)資料
型號： XC3S400AN-4FG400I
廠商： Xilinx Inc
文件頁數(shù)： 89/123頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN 3AN 400FBGA
標(biāo)準(zhǔn)包裝： 60
系列： Spartan®-3AN
LAB/CLB數(shù)： 896
邏輯元件/單元數(shù)： 8064
RAM 位總計(jì)： 368640
輸入/輸出數(shù)： 311
門數(shù)： 400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 400-BGA
供應(yīng)商設(shè)備封裝： 400-FBGA（21x21）
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
68
Table 61: Timing for the JTAG(2) Test Access Port
Symbol
Description
All Speed
Grades
Units
Min
Max
Clock-to-Output Times
TTCKTDO The time from the falling transition on the TCK pin to data appearing at the TDO pin
1.0
11.0
ns
Setup Times
TTDITCK
The time from the setup of data at the
TDI pin to the rising transition at the
TCK pin
All devices and functions except those shown below
7.0
–ns
Boundary-Scan commands (INTEST, EXTEST,
SAMPLE) on XC3S700AN and XC3S1400AN FPGAs
11.0
TTMSTCK The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin
7.0
–ns
Hold Times
TTCKTDI
The time from the rising transition at
the TCK pin to the point when data is
last held at the TDI pin
All functions except those shown below
0
–ns
Configuration commands (CFG_IN, ISC_PROGRAM)
2.0
TTCKTMS The time from the rising transition at the TCK pin to the point when a logic level is last held at the
TMS pin
0
–ns
Clock Timing
TCCH
The High pulse width at the TCK pin
All functions except ISC_DNA command
5
–ns
TCCL
The Low pulse width at the TCK pin
5
–ns
TCCHDNA The High pulse width at the TCK pin
During ISC_DNA command
10
10,000
ns
TCCLDNA The Low pulse width at the TCK pin
10
10,000
ns
FTCK
Frequency of the TCK signal
All operations on XC3S50AN, XC3S200AN, and
XC3S400AN FPGAs and for BYPASS or HIGHZ
instructions on all FPGAs
033
MHz
All operations on XC3S700AN and XC3S1400AN
FPGAs, except for BYPASS or HIGHZ instructions
20
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 10.
2.
For details on JTAG, see Chapter 9, “JTAG Configuration Mode and Boundary-Scan” in UG332 Spartan-3 Generation Configuration User
Guide.
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參數(shù)描述
XC3S400AN-4FG400I4100 制造商:Xilinx 功能描述:
XC3S400AN-4FGG400C 功能描述:IC SPARTAN-3AN FPGA 400K 400FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3AN 標(biāo)準(zhǔn)包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計(jì):221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241
XC3S400AN-4FGG400CES 制造商:Xilinx 功能描述:
XC3S400AN-4FGG400I 功能描述:IC FPGA SPARTAN-3A 400K 400-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3AN 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC3S400AN-4FT256C 制造商:Xilinx 功能描述:SPARTAN3AN - Trays 制造商:Xilinx 功能描述:IC FPGA SPARTAN-3AN 400K 256BGA 制造商:Xilinx 功能描述:IC FPGA 195 I/O 256FTBGA
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