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參數(shù)資料
| 型號(hào)： | XC3S100E-5VQG100C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 162/227頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA SPARTAN-3E 100K 100-VQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Spartan®-3E |
| LAB/CLB數(shù)： | 240 |
| 邏輯元件/單元數(shù)： | 2160 |
| RAM 位總計(jì)： | 73728 |
| 輸入/輸出數(shù)： | 66 |
| 門數(shù)： | 100000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-VQFP（14x14） |
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Spartan-3E FPGA Family: Introduction and Ordering Information
DS312 (v4.1) July 19, 2013
Product Specification
4
Configuration
Spartan-3E FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the
FPGA using any of seven different modes:
Master Serial from a Xilinx Platform Flash PROM
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
Byte Peripheral Interface (BPI) Up or Down from an
industry-standard x8 or x8/x16 parallel NOR Flash
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Boundary Scan (JTAG), typically downloaded from a
processor or system tester.
Furthermore, Spartan-3E FPGAs support MultiBoot
configuration, allowing two or more FPGA configuration
bitstreams to be stored in a single parallel NOR Flash. The
FPGA application controls which configuration to load next
and when to load it.
I/O Capabilities
The Spartan-3E FPGA SelectIO interface supports many
popular single-ended and differential standards. Table 2
shows the number of user I/Os as well as the number of
differential I/O pairs available for each device/package
combination.
Spartan-3E FPGAs support the following single-ended
standards:
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
3V PCI at 33 MHz, and in some devices, 66 MHz
HSTL I and III at 1.8V, commonly used in memory
applications
SSTL I at 1.8V and 2.5V, commonly used for memory
applications
Spartan-3E FPGAs support the following differential
standards:
LVDS
Bus LVDS
mini-LVDS
RSDS
Differential HSTL (1.8V, Types I and III)
Differential SSTL (2.5V and 1.8V, Type I)
2.5V LVPECL inputs
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
Package
VQ100
VQG100
CP132
CPG132
TQ144
TQG144
PQ208
PQG208
FT256
FTG256
FG320
FGG320
FG400
FGG400
FG484
FGG484
Footprint
Size (mm)
16x16
8x8
22x22
30.5x30.5
17x17
19x19
21x21
23 x 23
Device
User
Diff
User
Diff
User
Diff
User
Diff
User
Diff
User
Diff
User
Diff
User
Diff
XC3S100E
66(2)
9(7)
30
(2)
83
(11)
35
(2)
108
(28)
40
(4)
-
XC3S250E
66
(7)
30
(2)
92
(7)
41
(2)
108
(28)
40
(4)
158
(32)
65
(5)
172
(40)
68
(8)
-
XC3S500E
66(3)
(7)
30
(2)
92
(7)
41
(2)
-
158
(32)
65
(5)
190
(41)
77
(8)
232
(56)
92
(12)
-
XC3S1200E
-
190
(40)
77
(8)
250
(56)
99
(12)
304
(72)
124
(20)
-
XC3S1600E
-
250
(56)
99
(12)
304
(72)
124
(20)
376
(82)
156
(21)
Notes:
1.
All Spartan-3E devices provided in the same package are pin-compatible as further described in Module 4, Pinout Descriptions.
2.
The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins.
3.
The XC3S500E is available in the VQG100 Pb-free package and not the standard VQ100. The VQG100 and VQ100 pin-outs are identical
and general references to the VQ100 will apply to the XC3S500E.
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