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| 型號(hào)： | XC3S100E-5TQG144C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 208/227頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN-3E 100K 144-TQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Spartan®-3E |
| LAB/CLB數(shù)： | 240 |
| 邏輯元件/單元數(shù)： | 2160 |
| RAM 位總計(jì)： | 73728 |
| 輸入/輸出數(shù)： | 108 |
| 門(mén)數(shù)： | 100000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
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Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
81
read operations at this time. Spartan-3E FPGAs issue the
read command just once. If the SPI Flash is not ready, then
the FPGA does not properly configure.
If the 3.3V supply is last in the sequence and does not ramp
fast enough, or if the SPI Flash PROM cannot be ready
when required by the FPGA, delay the FPGA configuration
process by holding either the FPGA's PROG_B input or
INIT_B input Low, as highlighted in Figure 54. Release the
FPGA when the SPI Flash PROM is ready. For example, a
simple R-C delay circuit attached to the INIT_B pin forces
the FPGA to wait for a preselected amount of time.
Alternately, a Power Good signal from the 3.3V supply or a
system reset signal accomplishes the same purpose. Use
an open-drain or open-collector output when driving
PROG_B or INIT_B.
SPI Flash PROM Density Requirements
Table 57 shows the smallest usable SPI Flash PROM to
program a single Spartan-3E FPGA. Commercially
available SPI Flash PROMs range in density from 1 Mbit to
128 Mbits. A multiple-FPGA daisy-chained application
requires a SPI Flash PROM large enough to contain the
sum of the FPGA file sizes. An application can also use a
larger-density SPI Flash PROM to hold additional data
beyond just FPGA configuration data. For example, the SPI
Flash PROM can also store application code for a
MicroBlaze RISC processor core integrated in the
Spartan-3E FPGA. See Using the SPI Flash Interface after
CCLK Frequency
In SPI Flash mode, the FPGA’s internal oscillator generates
the configuration clock frequency. The FPGA provides this
clock on its CCLK output pin, driving the PROM’s clock input
pin. The FPGA starts configuration at its lowest frequency
and increases its frequency for the remainder of the
configuration process if so specified in the configuration
bitstream. The maximum frequency is specified using the
ConfigRate bitstream generator option. The maximum
frequency supported by the FPGA configuration logic
depends on the timing for the SPI Flash device. Without
examining the timing for a specific SPI Flash PROM, use
ConfigRate = 12 or lower. SPI Flash PROMs that support
the FAST READ command support higher data rates. Some
such PROMs support up to ConfigRate = 25 and beyond
but require careful data sheet analysis. See Serial
detailed timing analysis.
Using the SPI Flash Interface after Configuration
After the FPGA successfully completes configuration, all of
the pins connected to the SPI Flash PROM are available as
user-I/O pins.
If not using the SPI Flash PROM after configuration, drive
CSO_B High to disable the PROM. The MOSI, DIN, and
CCLK pins are then available to the FPGA application.
Because all the interface pins are user I/O after
configuration, the FPGA application can continue to use the
SPI Flash interface pins to communicate with the SPI Flash
PROM, as shown in Figure 56. SPI Flash PROMs offer
random-accessible, byte-addressable, read/write,
non-volatile storage to the FPGA application.
SPI Flash PROMs are available in densities ranging from
1 Mbit up to 128 Mbits. However, a single Spartan-3E
FPGA requires less than 6 Mbits. If desired, use a larger
SPI Flash PROM to contain additional non-volatile
application data, such as MicroBlaze processor code, or
other user data such as serial numbers and Ethernet MAC
IDs. In the example shown in Figure 56, the FPGA
configures from SPI Flash PROM. Then using FPGA logic
after configuration, the FPGA copies MicroBlaze code from
SPI Flash into external DDR SDRAM for code execution.
Similarly, the FPGA application can store non-volatile
application data within the SPI Flash PROM.
The FPGA configuration data is stored starting at location 0.
Store any additional data beginning in the next available SPI
Flash PROM sector or page. Do not mix configuration data
and user data in the same sector or page.
Similarly, the SPI bus can be expanded to additional SPI
peripherals. Because SPI is a common industry-standard
interface, various SPI-based peripherals are available, such
as analog-to-digital (A/D) converters, digital-to-analog (D/A)
converters, CAN controllers, and temperature sensors.
However, if sufficient I/O pins are available in the
application, Xilinx recommends creating a separate SPI bus
to control peripherals. Creating a second port reduces the
loading on the CCLK and DIN pins, which are crucial for
configuration.
The MOSI, DIN, and CCLK pins are common to all SPI
peripherals. Connect the select input on each additional SPI
peripheral to one of the FPGA user I/O pins. If HSWAP = 0
during configuration, the FPGA holds the select line High. If
HSWAP = 1, connect the select line to +3.3V via an external
4.7 k
Ω pull-up resistor to avoid spurious read or write
operations. After configuration, drive the select line Low to
select the desired SPI peripheral.
Table 57: Number of Bits to Program a Spartan-3E
FPGA and Smallest SPI Flash PROM
Device
Number of
Configuration Bits
Smallest Usable SPI
Flash PROM
XC3S100E
581,344
1Mbit
XC3S250E
1,353,728
2Mbit
XC3S500E
2,270,208
4Mbit
XC3S1200E
3,841,184
4Mbit
XC3S1600E
5,969,696
8Mbit
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| XC3S100E-5TQG144I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3E FPGA Family |
| XC3S100E-5VQ100C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3E 100K GATES 2160 CELLS 657MHZ 90NM 1.2V 100VT - Trays |
| XC3S100E-5VQ100GC | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3E FPGA Family: Complete Data Sheet |
| XC3S100E-5VQ100GI | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3E FPGA Family: Complete Data Sheet |
| XC3S100E-5VQ100I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3E FPGA Family: Complete Data Sheet |
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