參數(shù)資料
型號(hào)： XC3164A-3TQ144C
廠(chǎng)商： Xilinx Inc
文件頁(yè)數(shù)： 56/76頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 224 CLB'S 144-TQFP
產(chǎn)品變化通告： XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010
標(biāo)準(zhǔn)包裝： 60
系列： XC3000A/L
LAB/CLB數(shù)： 224
RAM 位總計(jì)： 46064
輸入/輸出數(shù)： 120
門(mén)數(shù)： 4500
電源電壓： 4.25 V ~ 5.25 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
其它名稱(chēng)： 122-1084
R
XC3000 Series Field Programmable Gate Arrays
7-8
November 9, 1998 (Version 3.1)
The input-buffer portion of each IOB provides threshold
detection to translate external signals applied to the pack-
age pin to internal logic levels. The global input-buffer
threshold of the IOBs can be programmed to be compatible
with either TTL or CMOS levels. The buffered input signal
drives the data input of a storage element, which may be
configured as either a flip-flop or a latch. The clocking
polarity (rising/falling edge-triggered flip-flop, High/Low
transparent latch) is programmable for each of the two
clock lines on each of the four die edges. Note that a clock
line driving a
rising edge-triggered flip-flop makes any latch
driven by the same line on the same edge Low-level trans-
parent and vice versa (
falling edge, High transparent). All
Xilinx primitives in the supported schematic-entry pack-
ages, however, are positive edge-triggered flip-flops or
High transparent latches. When one clock line must drive
flip-flops as well as latches, it is necessary to compensate
for the difference in clocking polarities with an additional
inverter either in the flip-flop clock input or the latch-enable
input. I/O storage elements are reset during configuration
or by the active-Low chip RESET input. Both direct input
(from IOB pin I) and registered input (from IOB pin Q) sig-
nals are available for interconnect.
For reliable operation, inputs should have transition times
of less than 100 ns and should not be left floating. Floating
CMOS input-pin circuits might be at threshold and produce
oscillations. This can produce additional power dissipation
and system noise. A typical hysteresis of about 300 mV
reduces sensitivity to input noise. Each user IOB includes a
programmable high-impedance pull-up resistor, which may
be selected by the program to provide a constant High for
otherwise undriven package pins. Although the Field Pro-
grammable Gate Array provides circuitry to provide input
protection for electrostatic discharge, normal CMOS han-
dling precautions should be observed.
Flip-flop loop delays for the IOB and logic-block flip-flops
are short, providing good performance under asynchro-
nous clock and data conditions. Short loop delays minimize
the probability of a metastable condition that can result
from assertion of the clock during data transitions. Because
of the short-loop-delay characteristic in the Field Program-
mable Gate Array, the IOB flip-flops can be used to syn-
chronize external signals applied to the device. Once
synchronized in the IOB, the signals can be used internally
without further consideration of their clock relative timing,
except as it applies to the internal logic and routing-path
delays.
IOB output buffers provide CMOS-compatible 4-mA
source-or-sink drive for high fan-out CMOS or TTL- com-
patible signal levels (8 mA in the XC3100A family). The net-
work driving IOB pin O becomes the registered or direct
data source for the output buffer. The 3-state control signal
(IOB) pin T can control output activity. An open-drain output
may be obtained by using the same signal for driving the
output and 3-state signal nets so that the buffer output is
enabled only for a Low.
Configuration program bits for each IOB control features
such as optional output register, logic signal inversion, and
3-state and slew-rate control of the output.
The program-controlled memory cells of Figure 4 control
the following options.
Logic inversion of the output is controlled by one
configuration program bit per IOB.
Logic 3-state control of each IOB output buffer is
determined by the states of configuration program bits
that turn the buffer on, or off, or select the output buffer
3-state control interconnection (IOB pin T). When this
IOB output control signal is High, a logic one, the buffer
is disabled and the package pin is high impedance.
When this IOB output control signal is Low, a logic zero,
the buffer is enabled and the package pin is active.
Inversion of the buffer 3-state control-logic sense
(output enable) is controlled by an additional
configuration program bit.
Direct or registered output is selectable for each IOB.
The register uses a positive-edge, clocked flip-flop. The
clock source may be supplied (IOB pin OK) by either of
two metal lines available along each die edge. Each of
these lines is driven by an invertible buffer.
Increased output transition speed can be selected to
improve critical timing. Slower transitions reduce
capacitive-load peak currents of non-critical outputs
and minimize system noise.
An internal high-impedance pull-up resistor (active by
default) prevents unconnected inputs from floating.
Unlike
the
original
XC3000
series,
the
XC3000A,
XC3000L, XC3100A, and XC3100L families include the
Soft Startup feature. When the configuration process is fin-
ished and the device starts up in user mode, the first activa-
tion of the outputs is automatically slew-rate limited. This
feature avoids potential ground bounce when all outputs
are turned on simultaneously. After start-up, the slew rate
of the individual outputs is determined by the individual
configuration option.
Summary of I/O Options
Inputs
-Direct
-
Flip-flop/latch
-
CMOS/TTL threshold (chip inputs)
-
Pull-up resistor/open circuit
Outputs
-
Direct/registered
-
Inverted/not
-
3-state/on/off
-
Full speed/slew limited
-
3-state/output enable (inverse)
Product Obsolete or Under Obsolescence
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