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參數(shù)資料
| 型號(hào)： | XC3164A-3TQ144C |
| 廠(chǎng)商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 18/76頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA 224 CLB'S 144-TQFP |
| 產(chǎn)品變化通告： | XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | XC3000A/L |
| LAB/CLB數(shù)： | 224 |
| RAM 位總計(jì)： | 46064 |
| 輸入/輸出數(shù)： | 120 |
| 門(mén)數(shù)： | 4500 |
| 電源電壓： | 4.25 V ~ 5.25 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 其它名稱(chēng)： | 122-1084 |
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R
November 9, 1998 (Version 3.1)
7-27
XC3000 Series Field Programmable Gate Arrays
7
Master Parallel Mode
In Master Parallel mode, the lead FPGA directly addresses
an industry-standard byte-wide EPROM and accepts eight
data bits right before incrementing (or decrementing) the
address outputs.
The eight data bits are serialized in the lead FPGA, which
then presents the preamble data (and all data that over-
flows the lead device) on the DOUT pin. There is an inter-
nal delay of 1.5 CCLK periods, after the rising CCLK edge
that accepts a byte of data, and also changes the EPROM
address, until the falling CCLK edge that makes the LSB
(D0) of this byte appear at DOUT. This means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy chain accepts data on the subsequent rising
CCLK edge.
X5990
RCLK
General-
Purpose
User I/O
Pins
M0 M1PWRDWN
M2
HDC
Other
I/O Pins
D7
D6
D5
D4
D3
D2
D1
D0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
+5 V
.....
CE
OE
FPGA
CCLK
DOUT
System Reset
A11
A12
A13
A14
A15
EPROM
RESET
...
Other
I/O Pins
DOUT
M2
HDC
LDC
FPGA
Slave #1
+5 V
M0 M1PWRDWN
CCLK
DIN
D/P
Reset
DOUT
FPGA
Slave #n
+5 V
M0 M1PWRDWN
CCLK
DIN
D/P
General-
Purpose
User I/O
Pins
RESET
Master
...
+5 V
8
INIT
...
M2
HDC
LDC
INIT
General-
Purpose
User I/O
Pins
+5 V
D/P
Other
I/O Pins
Note: XC2000 Devices Do Not
Have INIT to Hold Off a Master
Device. Reset of a Master Device
Should be Asserted by an External
Timing Circuit to Allow for LCA CCLK
Variations in Clear State Time.
Open
Collector
INIT
N.C.
Reprogram
5 k
5 k
5 k
5 k
Each
If Readback is
Activated, a
5-k
Resistor is
Required in
Series With M1
*
**
Figure 25: Master Parallel Mode Circuit Diagram
Product Obsolete or Under Obsolescence
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