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參數(shù)資料
| 型號： | XC3064L-8TQ144I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 31/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 3.3V I-TEMP 144-TQFP |
| 產(chǎn)品變化通告： | XC3000(L) Discontinuation 01/Feb/2003 |
| 標準包裝： | 60 |
| 系列： | XC3000A/L |
| LAB/CLB數(shù)： | 224 |
| RAM 位總計： | 46064 |
| 輸入/輸出數(shù)： | 120 |
| 門數(shù)： | 4500 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-TQFP（20x20） |
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November 9, 1998 (Version 3.1)
7-39
XC3000 Series Field Programmable Gate Arrays
7
AND of several slave mode devices, a hold-off signal for a
master mode device. After configuration this pin becomes a
user-programmable I/O pin.
BCLKIN
This is a direct CMOS level input to the alternate clock
buffer (Auxiliary Buffer) in the lower right corner.
XTL1
This user I/O pin can be used to operate as the output of an
amplifier driving an external crystal and bias circuitry.
XTL2
This user I/O pin can be used as the input of an amplifier
connected to an external crystal and bias circuitry. The I/O
Block is left unconfigured. The oscillator configuration is
activated by routing a net from the oscillator buffer symbol
output and by the MakeBits program.
CS0, CS1, CS2, WS
These four inputs represent a set of signals, three active
Low and one active High, that are used to control configu-
ration-data entry in the Peripheral mode. Simultaneous
assertion of all four inputs generates a Write to the internal
data buffer. The removal of any assertion clocks in the
D0-D7 data. In Master-Parallel mode, WS and CS2 are the
A0 and A1 outputs. After configuration, these pins are
user-programmable I/O pins.
RDY/BUSY
During Peripheral Parallel mode configuration this pin indi-
cates when the chip is ready for another byte of data to be
written to it. After configuration is complete, this pin
becomes a user-programmed I/O pin.
RCLK
During Master Parallel mode configuration, each change
on the A0-15 outputs is preceded by a rising edge on
RCLK, a redundant output signal. After configuration is
complete, this pin becomes a user-programmed I/O pin.
D0-D7
This set of eight pins represents the parallel configuration
byte for the parallel Master and Peripheral modes. After
configuration is complete, they are user-programmed I/O
pins.
A0-A15
During Master Parallel mode, these 16 pins present an
address output for a configuration EPROM. After configura-
tion, they are user-programmable I/O pins.
DIN
During Slave or Master Serial configuration, this pin is used
as a serial-data input. In the Master or Peripheral configu-
ration, this is the Data 0 input. After configuration is com-
plete, this pin becomes a user-programmed I/O pin.
DOUT
During configuration this pin is used to output serial-config-
uration data to the DIN pin of a daisy-chained slave. After
configuration is complete, this pin becomes a user-pro-
grammed I/O pin.
TCLKIN
This is a direct CMOS-level input to the global clock buffer.
This pin can also be configured as a user programmable
I/O pin. However, since TCLKIN is the preferred input to the
global clock net, and the global clock net should be used as
the primary clock source, this pin is usually the clock input
to the chip.
Unrestricted User I/O Pins
I/O
An I/O pin may be programmed by the user to be an Input
or an Output pin following configuration. All unrestricted I/O
pins, plus the special pins mentioned on the following page,
have a weak pull-up resistor that becomes active as soon
as the device powers up, and stays active until the end of
configuration.
Note:
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a weak
pull-up resistor.
Product Obsolete or Under Obsolescence
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