參數(shù)資料
型號: XC3064L-8TQ144C
廠商: Xilinx Inc
文件頁數(shù): 6/76頁
文件大?。?/td> 0K
描述: IC FPGA 3.3V C-TEMP 144-TQFP
產(chǎn)品變化通告: XC3000(L) Discontinuation 01/Feb/2003
標準包裝: 60
系列: XC3000A/L
LAB/CLB數(shù): 224
RAM 位總計: 46064
輸入/輸出數(shù): 120
門數(shù): 4500
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-TQFP(20x20)
R
XC3000 Series Field Programmable Gate Arrays
7-16
November 9, 1998 (Version 3.1)
Figure 15: Programmable Interconnection of Longlines. This is provided at the edges of the routing area.
Three-state buffers allow the use of horizontal Longlines to form on-chip wired AND and multiplexed buses. The left two
non-clock vertical Longlines per column (except XC3020A) and the outer perimeter Longlines may be programmed as
connectable half-length lines.
VCC
DA
DB
DC
DN
VCC
Z = DA DB DC ... DN
X3036
(LOW)
Figure 16: 3-State Buffers Implement a Wired-AND Function. When all the buffer 3-state lines are High, (high
impedance), the pull-up resistor(s) provide the High output. The buffer inputs are driven by the control signals or a Low.
D A
A
D B
B
D C
C
D N
N
D A A
+
=D B B
+ D C C
+
D N N
Z… +
X1741A
WEAK
KEEPER CIRCUIT
Figure 17: 3-State Buffers Implement a Multiplexer. The selection is accomplished by the buffer 3-state signal.
Product Obsolete or Under Obsolescence
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