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    參數(shù)資料
    

    


    


    
型號(hào)：
XC2S50-5PQG208C

    

    
廠商：
Xilinx Inc

    

    
文件頁(yè)數(shù)：
13/99頁(yè)

    

    
文件大?。?/td>
0K

    

    
描述：
IC SPARTAN-II FPGA 50K 208-PQFP

    

    
標(biāo)準(zhǔn)包裝：
24

    

    
系列：
Spartan®-II

    

    
LAB/CLB數(shù)：
384
    		

    

    
邏輯元件/單元數(shù)：
1728
    		

    

    
RAM 位總計(jì)：
32768
    		

    

    
輸入/輸出數(shù)：
140
    		

    

    
門數(shù)：
50000
    		

    

    
電源電壓：
2.375 V ~ 2.625 V
    		

    

    
安裝類型：
表面貼裝
    		

    

    
工作溫度：
0°C ~ 85°C
    		

    

    
封裝/外殼：
208-BFQFP
    		

    

    
供應(yīng)商設(shè)備封裝：
208-PQFP（28x28）
    		

    

    
產(chǎn)品目錄頁(yè)面：
599 (CN2011-ZH PDF)
    		

    

    
其它名稱：
122-1320
    		

    

    

    

	
    
    
    

    
    
	
    Spartan-II FPGA Family: Functional Description
    DS001-2 (v2.8) June 13, 2008
    Module 2 of 4
    Product Specification
    20
    R
    By default, these operations are synchronized to CCLK.
    The entire start-up sequence lasts eight cycles, called
    C0-C7, after which the loaded design is fully functional. The
    default timing for start-up is shown in the top half of
    Figure 13. The four operations can be selected to switch on
    any CCLK cycle C1-C6 through settings in the Xilinx
    software. Heavy lines show default settings.
    The bottom half of Figure 13 shows another commonly
    used version of the start-up timing known as
    Sync-to-DONE. This version makes the GTS, GSR, and
    GWE events conditional upon the DONE pin going High.
    This timing is important for a daisy chain of multiple FPGAs
    in serial mode, since it ensures that all FPGAs go through
    start-up together, after all their DONE pins have gone High.
    Sync-to-DONE timing is selected by setting the GTS, GSR,
    and GWE cycles to a value of DONE in the configuration
    options. This causes these signals to transition one clock
    cycle after DONE externally transitions High.
    Serial Modes
    There are two serial configuration modes: In Master Serial
    mode, the FPGA controls the configuration process by
    driving CCLK as an output. In Slave Serial mode, the FPGA
    passively receives CCLK as an input from an external agent
    (e.g., a microprocessor, CPLD, or second FPGA in master
    mode) that is controlling the configuration process. In both
    modes, the FPGA is configured by loading one bit per
    CCLK cycle. The MSB of each configuration data byte is
    always written to the DIN pin first.
    See Figure 14 for the sequence for loading data into the
    Spartan-II FPGA serially. This is an expansion of the "Load
    Configuration Data Frames" block in Figure 11. Note that
    CS and WRITE normally are not used during serial
    configuration. To ensure successful loading of the FPGA,
    do not toggle WRITE with CS Low during serial
    configuration.
    Figure 13: Start-Up Waveforms
    Start-up CLK
    Default Cycles
    Sync to DONE
    01
    2
    3
    4
    5
    6
    7
    01
    DONE High
    23
    4
    56
    7
    Phase
    Start-up CLK
    Phase
    DONE
    GTS
    GSR
    GWE
    DS001_13_090600
    DONE
    GTS
    GSR
    GWE
    Figure 14: Loading Serial Mode Configuration Data
    DS001_14_042403
    No
    Yes
    End of
    Configuration
    Data File?
    After INIT
    Goes High
    User Load One
    Configuration
    Bit on Next
    CCLK Rising Edge
    To CRC Check
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
XC2S50-5PQG208I
 制造商:Xilinx 功能描述:FPGA SPARTAN-II 50K GATES 1728 CELLS 263MHZ 2.5V 208PQFP - Trays

    

    
XC2S50-5TQ144C
功能描述:IC FPGA 2.5V 384 CLB'S 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）

    

    
XC2S50-5TQ144C-ES
 制造商:Xilinx 功能描述:2S50-5TQ144C-ES

    

    
XC2S50-5TQ144I
功能描述:IC FPGA 2.5V I-TEMP 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）

    

    
XC2S50-5TQG144C
功能描述:IC SPARTAN-II FPGA 50K 144-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計(jì):221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241

    

    
    
    
    
	
    	
    
    
     
     
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