參數(shù)資料
型號(hào)： XC2S200-5FG456I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 51/99頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 2.5V I-TEMP 456-FBGA
標(biāo)準(zhǔn)包裝： 60
系列： Spartan®-II
LAB/CLB數(shù)： 1176
邏輯元件/單元數(shù)： 5292
RAM 位總計(jì)： 57344
輸入/輸出數(shù)： 284
門數(shù)： 200000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 456-BBGA
供應(yīng)商設(shè)備封裝： 456-FBGA
Spartan-II FPGA Family: DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
Module 3 of 4
Product Specification
55
R
Global Clock Setup and Hold for LVTTL Standard, with DLL (Pin-to-Pin)
Global Clock Setup and Hold for LVTTL Standard, without DLL (Pin-to-Pin)
Symbol
Description
Device
Speed Grade
Units
-6
-5
Min
TPSDLL / TPHDLL
Input setup and hold time relative
to global clock input signal for
LVTTL standard, no delay, IFF,(1)
with DLL
All
1.7 / 0
1.9 / 0
ns
Notes:
1.
IFF = Input Flip-Flop or Latch
2.
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3.
DLL output jitter is already included in the timing calculation.
4.
A zero hold time listing indicates no hold time or a negative hold time.
5.
For data input with different standards, adjust the setup time delay by the values shown in "IOB Input Delay Adjustments for Different
Standards," page 57. For a global clock input with standards other than LVTTL, adjust delays with values from the "I/O Standard
Symbol
Description
Device
Speed Grade
Units
-6
-5
Min
TPSFD / TPHFD
Input setup and hold time relative
to global clock input signal for
LVTTL standard, no delay, IFF,(1)
without DLL
XC2S15
2.2 / 0
2.7 / 0
ns
XC2S30
2.2 / 0
2.7 / 0
ns
XC2S50
2.2 / 0
2.7 / 0
ns
XC2S100
2.3 / 0
2.8 / 0
ns
XC2S150
2.4 / 0
2.9 / 0
ns
XC2S200
2.4 / 0
3.0 / 0
ns
Notes:
1.
IFF = Input Flip-Flop or Latch
2.
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3.
A zero hold time listing indicates no hold time or a negative hold time.
4.
For data input with different standards, adjust the setup time delay by the values shown in "IOB Input Delay Adjustments for Different
Standards," page 57. For a global clock input with standards other than LVTTL, adjust delays with values from the "I/O Standard
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XC2S200-5FGG456C4124 制造商:Xilinx 功能描述:
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